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Interface IP

PLDA PCIe 6.0 Controller

The PLDA PCI Express (PCIe) 6.0 Controller (formerly XpressRICH) is configurable and scalable controller IP designed for ASIC implementation. The controller supports the PCIe 6.0 specification, including 64 GT/s data rates, PAM4 signaling, FLIT mode, and L0p power state. The PCIe 6.0 architecture will be essential for SoC designers creating next-generation chips that require the movement of large amounts of data within systems, including applications like HPC, cloud computing, artificial intelligence/machine learning (AI/ML), enterprise storage, networking, and automotive.

How the PCIe 6.0 Controller Works

The PCIe 6.0 controller is backward compatible to the PCIe 5.0, 4.0 and 3.1/3.0 specifications. It supports version 6.x of the PHY Interface for PCI Express (PIPE) specification. The controller exposes a highly efficient transmit (Tx) and receive (Rx) interface with configurable bus widths. Designed to satisfy a multitude of customer and industry use cases, the IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters.
PCIe 6.0 Controller Block Diagram
PCIe 6.0 Controller Block Diagram

The PCIe 6.0 controller is built on a flexible architecture that supports a variety of use cases that can be tailored to unique customer needs.

CXL Memory Interconnect Initiative: Enabling a New Era of Data Center Architecture

CXL Memory Interconnect Initiative: Enabling a New Era of Data Center Architecture

In response to an exponential growth in data, the industry is on the threshold of a groundbreaking architectural shift that will fundamentally change the performance, efficiency and cost of data centers around the globe. Server architecture, which has remained largely unchanged for decades, is taking a revolutionary step forward to address the growing demand for data and the voracious performance requirements of advanced workloads. 

Solution Offerings

Data Center Evolution: Accelerating Computing with PCI Express 5.0

Data Center Evolution: Accelerating Computing with PCI Express 5.0

The PCI Express® (PCIe) interface is the critical backbone that moves data at high bandwidth between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. The rise of cloud-based computing and hyperscale data centers, along with high-bandwidth applications like artificial intelligence (AI) and machine learning (ML), require the new level of performance of PCI Express 5.0.