The PCI Express® (PCIe®) 6.0 Controller is configurable and scalable controller IP designed for ASIC implementation. The controller supports the PCIe 6.0 specification, including 64 GT/s data rates, PAM4 signaling, FLIT mode, and L0p power state. The PCIe 6.0 architecture will be essential for SoC designers creating next-generation chips that require the movement of large amounts of data within systems, including applications like HPC, cloud computing, artificial intelligence/machine learning (AI/ML), enterprise storage, networking, and automotive.
The PCIe 6.0 Controller can be combined with the Rambus PCIe 6.0 PHY to make a complete PCIe 6.0 interface subsystem.
The PCIe 6.0 controller is built on a flexible architecture that supports a variety of use cases that can be tailored to unique customer needs.
The Rambus PCIe 6.0 Controller and Rambus PCIe 6.0 PHY together comprise a complete PCIe 6.0 Interface Subsystem.
The PCIe interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the torrid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.0 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard.
PCI Express layer
User Interface layer
Integrity and Data Encryption (IDE) – Optional
Unique Features & Capabilities
The PCI Express® (PCIe) interface is the critical backbone that moves data at high bandwidth between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. The rise of cloud-based computing and hyperscale data centers, along with high-bandwidth applications like artificial intelligence (AI) and machine learning (ML), require the new level of performance of PCI Express 5.0.