Home > Interface IP > PCI Express Interconnect Subsystem IP > PCIe 5.0 SerDes PHY
Designed with a minimal set of broadside controls, the PHY is configurable in x2, x4, x8 and x16 lane configurations with bifurcation support. This gives the PHY improved flexibility and support for a wide range of applications. Multi-tap transmitter and adaptive receiver equalization supports more than 36dB of channel insertion loss.
The PCIe 5 SerDes PHY is available on an advanced 7nm FinFET process node.
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Protocol | Signaling Rate (GT/s) | Application |
---|---|---|
PCIe 2.0 | 5 | High bandwidth peripherals and graphics |
PCIe 3.0 | 8 | Servers, storage, networking devices |
PCIe 4.0 | 16 | Servers, storage, networking devices |
PCIe 5.0 | 32 | AI, servers, storage, networking, 5G infrastructure |
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