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Interface IP

SerDes PHYs

Optimized for power and area, our line-up of SerDes PHYs deliver maximum performance and flexibility for today’s most challenging system applications.

SerDes Products Product Brief Protocol Application
PCIe 5.0 PHY Download PCIe PHY Product Brief  PCIe 5/4/3/2 Networking, 5G infrastructure, hyperscale data center
PCIe 4.0 PHY Download PCIe PHY Product Brief  PCIe 4/3/2 Peripherals, chip-to-chip connectivity, data center
32G USR/C2C PHY 1-32 Gbps Multi-protocol Server, networking, 5G infrastructure
32G PHY Download 32G PHY Product Brief 2.5-32 Gbps Multi-protocol Networking, 5G infrastructure, hyperscale data centers
28G PHY Download 28G PHY Product Brief 1.25-28 Gbps Multi-protocol Server, storage, networking
16G PHY Download 16G PHY Product Brief 1.25-16 Gbps Multi-protocol Enterprise, high-performance computing (HPC)
12G PHY Download 12G PHY Product Brief 1.25-12 Gbps Multi-protocol Networking, graphics, optical communications
6G PHY Download 6G PHY Product Brief 1.25-6.375 Gbps Multi-protocol Server, storage, networking
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Standards Compatible

Faster time-to-market

Multi-modal support

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Cost Effective

Flexible packaging options

Improved margin and yield

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Reduced Power

Wide range of PLL clock multipliers

Fine-grain power up/down options

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Improved Performance

Industry-leading data rates Higher bandwidth

SerDes Interfaces

Our SerDes interfaces are high-quality, complete PHY solutions that were designed with a system-oriented approach in mind to maximize flexibility and make them easy to integrate. They have been optimized for power and area at peak bandwidth and enable our customers to differentiate while maintaining complete compatibility with industry standards.

The SerDes interface family includes a range of solutions to meet your speed and application needs. Running up to 56gigabits per second (Gbps), our multi-protocol PHYs support server, storage, networking, graphics, and optical and communications applications.

SerDes PHY Configuration
SerDes PHY Configuration

What’s Included

We offer complete PHY solutions – our SerDes PHY includes a Physical Media Attachment (PMA) hard macro and Physical Coding Sub-layer with Built-in Self-Test (PCS-BIST) soft macro. That simplifies integration and minimizes time-to-market. The PHYs can also be configured to multiple channel widths and packaging options. Outside of the PHY itself, our solutions also include complete documentation and access to our in-house experts for optional design integration and bring-up support services to make integration as straightforward as possible.

SerDes Products 40nm Node 28nm Node 22nm Node 14nm Node 12nm Node 7nm Node
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Data Center Evolution: Accelerating Computing with PCI Express 5.0

Data Center Evolution: Accelerating Computing with PCI Express 5.0

The PCI Express® (PCIe) interface is the critical backbone that moves data at high bandwidth between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. The rise of cloud-based computing and hyperscale data centers, along with high-bandwidth applications like artificial intelligence (AI) and machine learning (ML), require the new level of performance of PCI Express 5.0. 

SerDes Signal Integrity Challenges at 28Gbps and Beyond

SerDes Signal Integrity Challenges at 28Gbps and Beyond

Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol. With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation.