|SerDes Products||Product Brief||Protocol||Application|
|PCIe 5.0 PHY||PCIe 5/4/3/2||Networking, 5G infrastructure, hyperscale data center|
|PCIe 4.0 PHY||PCIe 4/3/2||Peripherals, chip-to-chip connectivity, data center|
|112G LR PHY||10.3-106.25 Gbps Multi-protocol||Networking, 5G infrastructure, hyperscale data centers|
|112G XSR PHY||25-112 Gbps Multi-protocol||Die-to-die, die-to- optical engine interfaces for AI/ML, data center and networking|
|32G PHY||2.5-32 Gbps Multi-protocol||Networking, 5G infrastructure, hyperscale data centers|
|28G PHY||1.25-28 Gbps Multi-protocol||Server, storage, networking|
|16G PHY||1.25-16 Gbps Multi-protocol||Enterprise, high-performance computing (HPC)|
|12G PHY||1.25-12 Gbps Multi-protocol||Networking, graphics, optical communications|
|6G PHY||1.25-6.375 Gbps Multi-protocol||Server, storage, networking|
Flexible packaging options
Improved margin and yield
Wide range of PLL clock multipliers
Fine-grain power up/down options
Our SerDes interfaces are high-quality, complete PHY solutions that were designed with a system-oriented approach in mind to maximize flexibility and make them easy to integrate. They have been optimized for power and area at peak bandwidth and enable our customers to differentiate while maintaining complete compatibility with industry standards.
The SerDes interface family includes a range of solutions to meet your speed and application needs. Running up to 56gigabits per second (Gbps), our multi-protocol PHYs support server, storage, networking, graphics, and optical and communications applications.
We offer complete PHY solutions – our SerDes PHY includes a Physical Media Attachment (PMA) hard macro and Physical Coding Sub-layer with Built-in Self-Test (PCS-BIST) soft macro. That simplifies integration and minimizes time-to-market. The PHYs can also be configured to multiple channel widths and packaging options. Outside of the PHY itself, our solutions also include complete documentation and access to our in-house experts for optional design integration and bring-up support services to make integration as straightforward as possible.
The PCI Express® (PCIe) interface is the critical backbone that moves data at high bandwidth between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. The rise of cloud-based computing and hyperscale data centers, along with high-bandwidth applications like artificial intelligence (AI) and machine learning (ML), require the new level of performance of PCI Express 5.0.
Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol. With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation.