At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
|32G MPS PHY||32G SerDes PHY supporting up to long reach (LR) implementations for standards including JESD204B/C, CPRI™ and 100G Ethernet. Available on 22nm and 7nm process node|
|32G MR MPS PHY||Very low-power 32G SerDes PHY supporting up to medium reach (MR) implementations for standards including JESD204B/C, CPRI and Ethernet. Available on 7nm process node|
|32G MR PHY||Very low-power 32G SerDes PHY supporting up to medium reach (MR) implementations for standards including JESD204B/C, CPRI and Ethernet. Available on 12/16nm process node|
|32G C2C PHY||Extremely low power SerDes PHY solution for ultra-short reach (USR) and chip-to-chip (C2C) 32G interconnects. Available on 22 and 12/16nm process nodes|
|28G PHY||28G SerDes PHY supporting up to long reach (LR) implementations for standards including JESD204B/C, CPRI and 100G Ethernet. Available on 28/22/12nm process nodes|
|16G PHY||16G SerDes PHY supporting up to long reach (LR) implementations for standards including JESD204B/C, CPRI and 10G Ethernet. Available on 28/12nm process nodes|
|12G PHY||12G SerDes PHY supporting up to long reach (LR) implementations for standards including JESD204B/C, CPRI and 10G Ethernet. Available on 40/28nm process nodes|
|6G PHY||6G SerDes PHY supporting standards including Gigabit Ethernet. Available on 40nm process node|
The Rambus 32G MPS PHY is a comprehensive IP solution that is optimized for power and area in long-reach 30dB channels typical of communications, networking and data center applications. With high performance and multi-protocol compatibility, the PHY supports data rates from 2.5 to 32 Gbps in a wide range of industry-standard interconnect protocols including JESD204B/C, CPRI and Ethernet. It features application-specific optimization enabled by an efficient and scalable architecture with adaptive and programmable receive equalization, and support for transmit FIR adaptation.
The 32G MPS PHY is designed with a system-oriented approach, taking the interface, interconnect and channel into account when optimizing performance and features that maximize flexibility in today’s most challenging system environments. This makes the PHY ideal for high-performance wireline and 5G wireless infrastructure applications. The optional LabstationTM Software Environment is available for system bring-up, characterization, and validation.
For Ultra-Low Power 32G Designs
Rambus also offers an ultra-low power 32G MR MPS PHY for medium-reach channels up to 20dB insertion loss. This PHY solution supports PCIe 5.0 and earlier generations, Ethernet to 25.78125 Gbps, Interlaken, JESD 204B/C, CPRI and more. It offers the industry’s best power, area and latency in its class for next-generation applications with the most demanding PPA requirements. It is available on advanced FinFET process nodes.
Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1s and 0s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol. With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation.