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SerDes PHYs

Optimized for power and area, our line-up of SerDes PHYs deliver maximum performance and flexibility for today’s most challenging system applications.

SerDes ProductsProduct BriefProtocolApplication
PCIe PHY PCIe 2/3/4Peripherals, chip-to-chip connectivity, data centers
112G PHY 10.3-106.25 Gbps Multi-protocolNetworking, 5G infrastructure, hyperscale data centers
56G PHY 9.95-58 Gbps Multi-protocolNetworking, 5G infrastructure, hyperscale data centers
32G PHY 2.5-32 Gbps Multi-protocolNetworking, 5G infrastructure, hyperscale data centers
28G PHY 1.25-28 Gbps Multi-protocolServer, storage, networking
16G PHY 1.25-16 Gbps Multi-protocolEnterprise, high-performance computing (HPC)
12G PHY 1.25-12 Gbps Multi-protocolNetworking, graphics, optical communications
6G PHY 1.25-6.375 Gbps Multi-protocolServer, storage, networking
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Standards Compatible

Faster time-to-market

Multi-modal support

cost-effective icon

Cost Effective

Flexible packaging options

Improved margin and yield

Reduced Power

Wide range of PLL clock multipliers

Fine-grain power up/down options

high-performance icon

Improved Performance

Industry-leading data rates Higher bandwidth

SerDes Interfaces

Our SerDes interfaces are high-quality, complete PHY solutions that were designed with a system-oriented approach in mind to maximize flexibility and make them easy to integrate. They have been optimized for power and area at peak bandwidth and enable our customers to differentiate while maintaining complete compatibility with industry standards.

The SerDes interface family includes a range of solutions to meet your speed and application needs. Running up to 56gigabits per second (Gbps), our multi-protocol PHYs support server, storage, networking, graphics, and optical and communications applications.

SerDes PHY Configuration

SerDes PHY configuration

What’s Included

We offer complete PHY solutions – our SerDes PHY includes a Physical Media Attachment (PMA) hard macro and Physical Coding Sub-layer with Built-in Self-Test (PCS-BIST) soft macro. That simplifies integration and minimizes time-to-market. The PHYs can also be configured to multiple channel widths and packaging options. Outside of the PHY itself, our solutions also include complete documentation and access to our in-house experts for optional design integration and bring-up support services to make integration as straightforward as possible.

SerDes Products40nm Node28nm Node22nm Node14nm Node10nm Node
56G PHY 
32G PHY 
28G PHY  
16G PHY 
12G PHY  
SerDes Signal Integrity Challenges at 28Gbps and Beyond

SerDes Signal Integrity Challenges at 28Gbps and Beyond

Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol. With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation. For PAM4 signals, the baud rate equals one-half the bit rate and the Nyquist frequency equals one-fourth the bit rate. Compared to PAM2/NRZ, PAM4 cuts the bandwidth for a given data rate in half by transmitting two bits in each symbol. This allows engineers to double the bit rate in the channel without doubling the required bandwidth.
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