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Interface IP

112G LR Multi-protocol SerDes PHY

An ADC-based long-reach (LR) 112G SerDes PHY solution providing leading-edge performance and power efficiency for next-generation networking and hyperscale data center applications.

How the 112G LR PHY works

The Rambus 112G LR MPS PHY is a comprehensive IP solution designed to provide best-in-class performance across challenging long-reach signaling environments for next-generation networks and hyper-scale data centers. It supports PAM-4 and NRZ signaling and data rates from 10.31 to 106.25 Gbps across copper and backplane channels with more than 35dB insertion loss. At the heart of the 112G MPS architecture is an ADC operating at 56 GS/s that allows for adjustable power and improved performance while providing low BER.

112G SerDes PHY Subsystem Example
112G SerDes PHY Subsystem Example

The 112G LR MPS PHY is designed with a system-oriented approach, maximizing flexibility in today’s most challenging system environments including 100 to 800 GbE, as well as 112G chip-to-chip (C2C) and chip-to-module (C2M) applications.

Available in advanced 7nm FinFET process.

Solution Offerings

Protocol Compatibility

ProtocolData Rate (Gbps) Application
400GBASE-KR106.25Telecom and networking
400GAUI-4 C2C/C2M106.25Telecom and networking
200GBASE-KR53.125Telecom and networking
200GAUI-4 C2C/C2M53.125Telecom and networking
100GBASE-KR25.78125Telecom and networking
10G-KR LR10.3125Telecom and networking
CEI112G-VSR/MR/LR75 – 116C2C, C2M, copper backplane networking
CEI56G-MR/LR36 – 58C2C, C2M, copper backplane networking
CEI28G-MR19.9 – 28.1Copper backplane networking
CEI25G-LR19.9 – 25.8Copper backplane networking
CEI11G-LR9.95 – 11.2Copper backplane networking
Rambus 112G XSR and LR SerDes PHYs eBook cover

Rambus 112G XSR and LR SerDes PHYs

The virtuous cycle of increased computing power enabling new applications which demand more computing power continues unabated. Today, applications spanning AI, autonomous vehicles, video streaming, AR and VR all demand more bandwidth, lower latencies and higher speeds. In response, the SoCs powering the terabit routers and switches at the heart of the network must run even faster. The upgrade to 112G SerDes represents the latest advancement in high-speed signaling technology enabling communication within and between network devices.

Inventions

Phase Interpolator-Based CDR

Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.