112G LR MPS PHY Subsystem Example
The 112G LR MPS PHY is designed with a system-oriented approach, maximizing flexibility in today’s most challenging system environments including 100 to 800 GbE, as well as 112G chip-to-chip (C2C) and chip-to-module (C2M) applications.
Available in advanced 7nm FinFET process.
Comprehensive chip and system design reviews
Engineering design services:
|Protocol||Data Rate (Gbps)||Application|
|400GBASE-KR||106.25||Telecom and networking|
|400GAUI-4 C2C/C2M||106.25||Telecom and networking|
|200GBASE-KR||53.125||Telecom and networking|
|200GAUI-4 C2C/C2M||53.125||Telecom and networking|
|100GBASE-KR||25.78125||Telecom and networking|
|10G-KR LR||10.3125||Telecom and networking|
|CEI112G-VSR/MR/LR||75 – 116||C2C, C2M, copper backplane networking|
|CEI56G-MR/LR||36 – 58||C2C, C2M, copper backplane networking|
|CEI28G-MR||19.9 – 28.1||Copper backplane networking|
|CEI25G-LR||19.9 – 25.8||Copper backplane networking|
|CEI11G-LR||9.95 – 11.2||Copper backplane networking|
The virtuous cycle of increased computing power enabling new applications which demand more computing power continues unabated. Today, applications spanning AI, autonomous vehicles, video streaming, AR and VR all demand more bandwidth, lower latencies and higher speeds. In response, the SoCs powering the terabit routers and switches at the heart of the network must run even faster. The upgrade to 112G SerDes represents the latest advancement in high-speed signaling technology enabling communication within and between network devices.
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