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Interface IP


A high-bandwidth, ultra-low power SerDes PHY solution for extra short reach (XSR) and very short reach (VSR) 56G die-to-die (D2D), die-to-optical-engine (D2OE) and chip-to-module connections for devices serving AI/ML, data center and networking applications.

How the 56G XSR/VSR PHY works

The Rambus 56G XSR/VSR PHY is a comprehensive IP solution designed to provide best-in-class performance for the high-bandwidth connections between die or chiplets in SiP devices, as well as between modules. The 56G MPS PHY supports PAM-4 (XSR and VSR) and NRZ (XSR) signaling. It is tailored for the ultra-low power and area requirements of short reach interfaces.
56G XSR/VSR SerDes PHY Subsystem Example
56G XSR/VSR SerDes PHY Subsystem Example

The 56G XSR/VSR PHY is designed with a system-oriented approach, maximizing flexibility in today’s most challenging system environments including specifically:

  • Die-to-die (D2D) interfaces
  • Die-to-optical engine (D2OE) interfaces
  • Chip-to-module interfaces


Available in advanced 7nm FINFET process.

For long and medium reach applications, Rambus offers the 56G Multi-protocol SerDes PHY.

Rambus 112G XSR and LR SerDes PHYs eBook cover

Rambus 112G XSR and LR SerDes PHYs

The virtuous cycle of increased computing power enabling new applications which demand more computing power continues unabated. Today, applications spanning AI, autonomous vehicles, video streaming, AR and VR all demand more bandwidth, lower latencies and higher speeds. In response, the SoCs powering the terabit routers and switches at the heart of the network must run even faster. The upgrade to 112G SerDes represents the latest advancement in high-speed signaling technology enabling communication within and between network devices.

Solution Offerings

  • Supports up to 8 duplex lanes and data rates from 25 to 56 Gbps with scalability to 112 Gbps
  • Ultra-low power configurable architecture for D2D, D2OE and chip-to-module interfaces
  • Design flexibility allows for placement along all ASIC edges in an ASIC
  • Programmable TX/RX equalizers including: Multi-tap digital FFE and CTLE
  • A centralized LC-PLL supports a wide range of reference clock frequencies and lane operating frequencies
  • PMA is spec. compliant across a wide operating junction temperature range (-20 to 105 °C). PLLs, bias circuits, and data paths are functional between -40 to 125 °C
  • In-situ real-time monitoring and receive data eye voltage histogram
  • Built in PRBS generators and checkers along with custom pattern generation
  • ATPG Mux Scan support for digital logic
  • IEEE 1149.6 JTAG boundary scan for SerDes pins
  • Built-in BER monitor including a 40-bit counter to count the total number of bits received and a 30-bit counter to count the total number of errors detected by a pattern checker
  • Internal serial loopback and parallel loopback support
  • Interfaces available for connection to a JTAG TAP controller or through a simple parallel read/write port
  • PMA Hard Macro and Design Kit
    • Verilog models
    • LEF abstracts (.lef)
    • Timing models (.lib)
    • CDL netlists (.cdl)
    • ATPG models
    • IBIS-AMI models
    • GDSII layout
    • DRC and LVS reports
  • Datasheet
  • SoC integration guide
  • Optional design integration and bring-up support services

Protocol Compatibility

ProtocolData Rate (Gbps) Application
CEI56G-XSR-NRZ36-58AI/ML, data center and networking
CEI56G-XSR36-58AI/ML, data center and networking
CEI56G-VSR36-58AI/ML, data center and networking
CEI28G-VSR19.6-28.1Data center and networking


Phase Interpolator-Based CDR

Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.