Interface IP
6G Multi-protocol SerDes PHY
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Product BriefHow the 6G PHY works
The Rambus 6G Multi-protocol SerDes (MPS) PHYs are a general-purpose, high-speed serial link subsystem that support data rates from 1.25 Gbps to 6.375 Gbps. Optimized for power and area, they can compete even with single-protocol solutions.
The PHYs include a PMA hard macro that supports a broad range of networking protocols and a PCS-BIST soft macro for PCIe that is PIPE4 compliant. They have a minimal set of broadside control and is configurable in x2, x4 and x8 lane configurations. This gives the PHYs improved flexibility and support for a wide range of applications.
MPSL Subsystem Example
The 6G PHYs feature Built-in-self-test (BIST) with PRBS checker functionality, transmit and receive equalization, and supports a wide range of reference clock multipliers to improve system margin and performance. This ensures the best signal quality and enables greater design flexibility.
Available on TSMC and Global Foundry process nodes.
SerDes Signal Integrity Challenges at 28Gbps and Beyond
Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol. With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation.
Solution Offerings
- Duplex lane configurations of x1, x2, x4, and x8
- Transmit swing of at least 800 mV differential peak-to-peak
- Support for AC-coupled interfaces
- Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
- BER of less than 10-15 at 6.375 Gbps
- A wide range of PLL multiplication supporting low reference clock frequencies
- Flexible ASIC clocking
- Tight skew control of 2UI between lanes of the PMA
- One-tap transmit equalizer with multi-level de-emphasis
- Supports PCIe and CEI6-SR de-emphasis settings
- Receive linear equalizer with programmable settings providing up to 8dB gain at 6.4Gbps
- Expandable register interface enabling communication with multiple PMAs and PCS-BIST soft macros
- Built-in Self Test (BIST) with ATPG and AC/DC boundary scan support
- Built-in PRBS pattern generation and checking for standalone loopback testing
- In-situ real-time monitoring and receive data eye schmoo
- Operation across a wide temperature range (-40 C to +125 C
- PMA Hard Macro
- Verilog models
- LEF abstracts (.lef)
- Timing models (.lib)
- CDL netlists (.cdl)
- ATPG models
- IBIS-AMI models
- GDSII layout
- DRC & LVS reports
- PCS-BIST Soft Macro
- RTL model
- Datasheet
- SoC Integration guide
- Optional design integration and bring-up support services
Comprehensive Chip and System Design Reviews
- Kickoff/Program Review
- Floor plan Review
- Test/Characterization Plan Review
- Package Design Review
- Board Design Review
- Final Chip Integration Review
- Bring-up and Test Review
Engineering Design Services:
- Package design
- System board layout
- Statistically-based signal and power integrity analysis
Protocol Compatibility
| Protocol | Data Rate (Gbps) | Application |
|---|---|---|
| PCIe1/2/3 | 2.5, 5 | Graphics cards and high-bandwidth peripherals |
| SATA 1/2/3 | 1.5, 3, 6 | Personal computing and server storage |
| GbE | 1.25 | Backplane and copper cable networking |
| XAUI/2xXAUI | 3.125,6.25 | Networking |
| CEI6-SR | 4.976-6.375 | Telecom and networking |
| USB 2/3 | 0.4, 5 | Computing and peripheral connectivity |
| Interlaken | 4.976-6.375/td> | Networking |
Inventions
Phase Interpolator-Based CDR
Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.
Resources
Videos
