Memory + Interfaces

16 Gbps Multi-protocol SerDes PHY

The 16 Gbps Multi-protocol SerDes PHYs, including recently acquired Snowbush IP,  are designed to maximize interface speed in the difficult system environments found in Big Data and cloud applications. It is a complete solution designed with a system-oriented approach to maximize flexibility and ease integration for our customers.

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Product Brief

R+ 1.25-16 Gbps Multi-protocol Serial Link PHY block diagram

16G PHY Subsystem Example

How it works

The Rambus 16 Gbps Multi-Protocol SerDes (MPS) PHYs are a high-performance serial link subsystem. Optimized for power and area in challenging, high-loss channels typical of copper backplanes and long runs of cable, our 16G MPS PHYs are ideal for networking, telecom and data center systems.

The PHYs come complete with a PMA hard macro that supports a broad range of protocols and a PCS soft macro for PCIe that is PIPE4.2 compliant. They have a minimal set of broadside control and are configurable in x2, x4 and x8 lane configurations. This gives the PHYs improved flexibility and support for a wide range of applications.

In order to improve system margin and performance, our solution features transmit and receive equalization, data rate negotiation, and equalization adaptation. This ensures that data is recovered even in the presence of channel and system interference.

Available on TSMC, Global Foundry and Samsung process nodes.

Solution Offerings

Protocol Compatibility

Protocol Data Rate (Gbps) Application
PCIe 2.5, 5, 8, 16 Graphics cards and high-bandwidth peripherals
SATA 1.5,3,6 Storage connectivity
SAS 3, 6, 12 Server systems storage
10GBase-KR 10.3125 Copper backplane networking
1000Base-KX 1.25 Backplane and copper cable networking
10GBase-KX4 3.125, 6.25 Copper backplane networking
XAUI/2xXAUI 3.125, 6.25 Chip-to-Chip connectivity
CEI6-SR 4.976-6.375 Telecom and networking
CEI11-SR, LR 9.95-11.2 Telecom and networking
XFI 9.95-11.2 XFP and SFP+ Optical Modules
Interlaken 6 G & 10 G 4.976-6.375, 10.3125 Networking
HMC 2.0 15 High performance computing
Fibre Channel 4.25/8.5/14.025 Enterprise storage
JESD204B/C 12.5-16.3 High-speed data converters connectivity
CPRI v5.6 1.2288-10.1376 Wireless Base Stations

Inventions

Phase Interpolator-based CDR

Phase-Interpolator-based-Clock-and-Data-Recovery-CDR-thumbnail

Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.

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Data Center