Memory + Interfaces

56 Gbps Multi-protocol SerDes PHY

The 56 Gbps Multi-protocol SerDes PHYs is a comprehensive PAM-4 solution with available adjustable power through an integrated ADC that provides for future scalability in long-reach data center applications

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Product Brief

R+ 1.25-16 Gbps Multi-protocol Serial Link PHY block diagram

56G PHY Subsystem Example

How it works

The Rambus 56 Gbps Multi-Protocol SerDes (MPS) PHYs are a PAM-4 and NRZ compliant IP solutions that provide reliable performance across challenging long-reach data center environments. A 28 GS/s ADC integrated directly into the architecture enables future scalability and extended reach. With high performance and multi-protocol compatibility, the PHYs support data rates from 9.95Gbps to 58Gbps across copper and backplane channels with more than 35dB channel insertion loss in a wide range of industry-standard interconnect protocols. Flexible system design is enabled through the ability to control the power consumption of the PHY.

The 56G MPS are designed with a system-oriented approach, taking the interface, interconnect and channel into account when optimizing performance and features to maximize flexibility in today’s most challenging system environments and applications. This makes the PHYs ideal for many long-reach, copper and backplane enterprise environments.

Available in an advanced FINFET Process

Solution Offerings

Protocol Compatibility

Protocol Data Rate (Gbps) Application
400GAUI-8 LR 53.125 Telecom and networking
400GAUI-8 MR 53.125 Telecom and networking
100G-KR4 LR 25.78125 Telecom and networking
10G-KR 10.3125 Telecom and networking
CEI56G-LR 36 – 58 Copper backplane networking
CEI56G-MR 36 – 58 Chip-to-Chip connectivity
CEI28G-MR 19.9 – 28.1 Copper backplane networking
CEI25G-LR 19.9 – 25.8 Copper backplane networking
CEI11G-LR 9.95 – 11.2 Copper backplane networking

Inventions

Phase Interpolator-based CDR

Phase-Interpolator-based-Clock-and-Data-Recovery-CDR-thumbnail

Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.

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