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CryptoManager Root of Trust RT-640

The CryptoManager Root of Trust RT-640 is a fully programmable, ISO-26262 ASIL-B ready hardware security core offering security by design for automotive applications. It protects against a wide range of failures such as permanent, transient and latent faults and hardware and software attacks with state-of-the-art anti-tamper and security techniques.

As the connected nature of automobiles evolves, device architects face a growing array of emerging security threats. Whether V2X, ADAS, infotainment, or other application, one constant in automotive design is the need for a hardware root of trust-based security implementation. The Rambus RT-640 is the ideal security co-processor for automotive uses. Built on a custom 32-bit RISC-V siloed and layered secure co-processor, along with dedicated secure memories, the RT-640 features a number of high-capability cryptographic accelerators like AES (all modes), HMAC, SHA-2 (all modes), RSA up to 4096 bits, ECC up to 521 bits, a NIST-compliant Random Bit Generator, AXI Multi Issue Out-of-Order, and Fast DMA capability. Additional algorithms such as Whirlpool (SHE), SHA-1 (legacy), AES-CMAC, SHA-3, Poly1305 & ChaCha and OSCCA SM2-3-4 are available as optional HW crypto accelerators.

Additionally, the RT-640 is certified by TÜV-SGS as ISO26262 ASIL-B ready satisfying the ASIL-B Single Point Fault Metric (SPFM ≥ 90 % of faults detected) and Latent Fault Metric (LFM ≥ 60 % of faults detected). To support customers, the RT-640 package comes with the proper ASIL documentation, such as the ASIL-B Failure Modes Effects and Diagnostic Analysis (FMEDA and Safety manuals.

Satisfying use cases such as secure boot, EVITA HSM, and protection of propriety algorithms, the ISO-26262 ASIL-B ready RT-640 is ideally suited for automotive applications where security is imperative. If higher SPFM and LFM rates are required, the RT-645 ASIL-D ready configuration is available.

How the Root of Trust Works

The CryptoManager Root of Trust RT-640 is an independent hardware security co-processor design for integration into semiconductor devices, offering secure execution of user applications, tamper detection and protection, and secure storage and handling of keys and security assets. The Root of Trust offers chipmakers a siloed approach to security; while located on the same silicon as the main processor, the secure processing core is physically separated. A layered security approach enforces access to crypto modules, memory ranges, I/O pins, and other resources, and assures critical keys are available through hardware only with no access by software. While based on a custom processor, the CryptoManager Root of Trust supports all common main processor architectures, including ARM, RISC-V, x86 and others.

CryptoManager Root of Trust

The CryptoManager Root of Trust supports multi-tenant deployments by offering true multiple root of trust capabilities. Each individual Secure Application can be assigned its own unique keys, meaning permissions and access levels are set completely independent of others. Secure Applications are siloed from each other, ensuring the best approach to security. OEMs can determine access levels and permissions for each and all processes operating within the secure processor.

Secure Applications

Included with the RT-640 Hardware Root of Trust are a series of standard secure applications (“containers”) to speed development, including secure boot, identity management, HSM reference, and others. Dedicated EVITA-Full and EVITA-Medium Secure Applications can be offered on request. A container development kit (CDSK) is also included to allow the development of custom containers for specific use cases.

The Road to Post Quantum Cryptography cover

The Road to Post Quantum Cryptography

Quantum computing offers the promise of tremendous leaps in processing power over current digital computers. But for the public-key cryptography algorithms used today for e-commerce, mobile payments, media streaming, digital signatures and more, quantum computing represents an existential event. Quantum computers may be able to break the widely used RSA and ECC (Elliptic-Curve Cryptography) algorithms in as little as days. Work on Post Quantum Cryptography (PQC) is well under way, but implementation will come with its own set of challenges. Rambus has solutions and recommendations to ready customers for a post-quantum world.

Solution Offerings

Superior Security

  • Hardware root of trust built on a custom 32-bit RISC-V processor
  • Secure in-core processing and industry-leading anti-tamper protections
  • Built-in tamper detection and resistance to side-channel attacks (configuration-dependent)
  • Multi-layered security model provides protection of all components in the core
  • FIPS 140-2 & 140-3 CAVP certified
  • FIPS 140-2 & 140-3 CMVP certified

Enhanced Flexibility

  • 3rd-party applications run securely within trusted boundary, each with its own assigned security permissions
  • Complete development environment allows OEMs and users to easily develop secure applications (”containers”); standard use case application containers provided
  • Support for secure provisioning of keys and firmware at manufacturing or in the field
  • Support for multiple roots of trust within a single secure core

Security Models

  • Hierarchical privilege
  • Secure key management policy
  • Hardware-enforced isolation/access control/protection
  • Error management policy

Cryptographic Accelerators

  • Includes AES, HMAC, RSA, ECC, RBG (configuration-dependent)

Security Modules

  • Canary logic for protection against glitching and overclocking
  • Secure key derivation and key transport
  • Life cycle management
  • Secure test and debug
  • Feature management

Complete Documentation

  • Hardware integration guide
  • Hardware and software reference manuals
  • Programming guides

Tools and Scripts

  • Verilog for synthesis and simulation
  • All scripts and support files needed for standard EDA tool flows integration deliverables

Integration Deliverables

  • Complete verification test bench and comprehensive set of test vectors
  • Container-authoring software
  • Boot loader and firmware, including secure RTOS and security monitor
  • HLOS APIs for accessing capabilities
  • Complete development environment, including compiler, assembler, debugger, simulator, reference code
  • Available FGPA-based development board

Secure Applications Deliverables

  • QEMU implementation (source code)
  • Implementation of HLOS or ASIC components (source code)
  • Sample application demonstrating usage of Secure Application
  • Documentation
    • Software Architecture
    • HLOS Programmer’s Guide
    • Developer’s Guide
    • API Guide
    • Integration Guide
Secure ApplicationDescription
Linux Secure BootImplements secure boot for Linux OS, secured by the Root of Trust co-processor
Linux Secure FOTAImplements secure Firmware Over the Air (FOTA) updates for Linux OS
ASIC Secure BootUses the Root of Trust co-processor to assist in the secure boot process of ASICs and FPGAs
Secure Data StorageUses the Root of Trust co-processor to protect user credentials or biometric templates
Open SSL HardeningHardens the OpenSSL crypto operations via the Root of Trust secure co-processor
Reference HSMImplements a basic HSM supporting AES, HMAC, SHA256, ECDSA, X.509 certificates and secure storage
Unique ID GeneratorCreates a Root of Trust unique ID and stores it in the Root of Trust NVM (Non Volatile Memory)
Full Disk Encryption of Solid State Drives and Root of Trust Cover

Full Disk Encryption of Solid State Drives and Root of Trust

File encryption, file system encryption and full disk encryption (FDE) are methods offered by the industry to allow users to protect their data stored on non-volatile storage devices, such as Solid State Disks (SSD). The main feature of FDE is to protect stored system and user date from unauthorized reading, writing, alteration, moving or rolling back. However, extended security features are key to securing FDE implementation.

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