Lou Ternullo, Senior Director of IP Product Management at Rambus, discusses the critical role of PCIe and CXL interconnects in enabling the AI-driven data centers of tomorrow. He explores the challenges of traditional server setups, such as inefficiencies in resource allocation, over-provisioning, and data replication, and presents disaggregation as a solution to improve cost-efficiency and performance. By leveraging PCIe and CXL interconnects, data centers can enable heterogeneous compute, memory sharing, and lower-latency communication across servers and racks. Lou underscores the importance of these interconnect technologies in reducing latency, optimizing resource use, and lowering costs in AI-focused data centers.
Interface IP
Why Memory Matters for AI
In this roundtable discussion, memory experts Steve Woo, John Eble, and Nidish Kamath explore the critical role of memory in AI applications. They discuss how AI’s rapid evolution, especially with the growth of large language models, is driving the need for higher memory capacity, bandwidth, and power efficiency.
The Impact of AI 2.0 on Memory & Interconnect Technology
Steven Woo, Fellow and Distinguished Inventor at Rambus Labs, explores the transformative impact of AI 2.0 on memory and interconnect technology. He highlights how the rapid growth of AI models, exceeding trillions of parameters, and the shift to multimodal systems has dramatically increased the demand for higher memory capacity and bandwidth. He discusses the critical role of efficient data movement, the challenges in powering high-performance AI systems, and the importance of security as the value of AI models continues to rise.
Unlocking the Potential of CXL 3.1 and PCIe 6.1 for Next-Generation Data Centers
[Live on Feb 28] Increased demand for bandwidth, capacity and compute, coupled with the implications for increased data center costs, are the realities of the AI revolution. This is driving the need for new disaggregated architectures in the data center. Join Lou Ternullo to learn about how PCIe 6.1 and CXL 3.1 interfaces are evolving to address the needs of the next-generation data center.
LPDDR5X: Delivering High Bandwidth and Power Efficiency
The bandwidth and low power characteristics of LPDDR make it an increasingly attractive choice of memory for applications in IoT, automotive, and edge computing. LPDDR5X takes performance to the next level with a data rate of up to 8.5 Gbps. Join Vinitha Seevaratnam to learn which applications can benefit from using LPDDR memory.
System Level Design Considerations for PCIe 6.0
PCIe 6.0 offers many new and exciting features including a 64 GT/s data rate, PAM4 signaling, forward error correction, and a low power L0p mode. In this presentation, Lou Ternullo will walk you through all the system design considerations you will need to know before getting started on your PCIe 6.0 design, including how to get the most out of each of the PCIe devices.
