Compute Express Link™ (CXL) has evolved rapidly since its launch in 2019 and is slated for debut in the next generation of server platforms coming later this year. While it builds on the same physical layer as PCI Express, CXL implements unique features at the controller level to enable memory cache coherency between a host and multiple types of connected devices including smart NICs, accelerators and memory expansion devices.
Interface IP
Memory Bandwidth for AI/ML Races Higher with HBM3
With the insatiable need for higher bandwidth in state-of-the-art AI/ML training and HPC, the HBM standard has been on a rapid pace of improvement. The newly standardized HBM3 generation doubles the data rate to 6.4 Gb/s that offers up to 819 GB/s of memory bandwidth between an accelerator and a single HBM3 DRAM device. Memory interface technology expert, Frank Ferro will discuss how the Rambus 8.4 Gb/s HBM3 Memory Subsystem can provide the headroom and scalability needed for implementing state-of-the-art HBM designs.
Advancing Computing in the Accelerator Age
Moore’s Law has been the force that has shaped the modern world enabling chips with billions of transistors. Yet today, when we need Moore’s Law more than ever, the rate of semiconductor scaling is slowing, requiring system architects to take a new approach to continue the pace of performance gains in computing. Heterogenous compute architectures with purpose-built silicon hold the key to the next great chapter of semiconductor industry as we enter the accelerator era.
Memory Bandwidth Races Higher with HBM3
Join memory expert Frank Ferro for a live webinar as he discusses what changes come with the new generation of HBM, and how the Rambus HBM3 memory subsystem can help designers unleash the full power of their HBM3-enabled accelerators and SoCs.
Bring on the Bandwidth with HBM3 Memory
Join memory interface technology expert Frank Ferro as he discusses the capabilities of, and design considerations for, the upcoming 3rd- generation of high-bandwidth memory: HBM3.
CXL and IDE: Important Considerations of Protecting High Speed Interconnects
Hear Rambus and Siemens discuss the background of IDE, the threat models it addresses, and how zero latency IDE’s can provide assurances to CXL adopters. Design and verification engineers and managers won’t want to miss this webinar to understand how to incorporate and validate this essential standard in their designs.
