Rambus @ DesignCon 2022

Join us at DesignCon for a full-day training session on Wednesday, April 6th! Our sessions will cover the future of data centers and evolution of memory systems, 2.5D/3.D architecture solutions, automotive security, as well as IP solutions including CXL, HBM3, GDDR6, and PCIe 6.0 interfaces. All sessions will be in Great America 1.

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Technical Training Agenda

TimeSession Information
8:00am – 8:45am

Future Data Centers and the Evolution of Memory Systems

Speaker: Steven Woo, Fellow and Distinguished Inventor, Rambus
Abstract: The world’s connectivity continues to increase, and the importance of digital data continues to grow. The unprecedented rise in data volumes is matched in importance by the value being extracted from this data. Server and data center architectures are evolving in response to the growing volume and importance of digital data, and greater intelligence is moving to the edge of the network and to the end points themselves. Data movement and power efficiency join a growing list of challenges as architects look to address bandwidth and capacity needs for future data centers.

9:00am – 9:45am

GDDR6 Memory Enables High-Performance Inferencing

Speaker: Frank Ferro, Senior Director of Product Management, Rambus Interface IP
Abstract: A rapid rise in the size and sophistication of inferencing models has necessitated increasingly powerful hardware deployed at the network edge and in the endpoint devices. To keep these inferencing processors and accelerators fed with data requires a state-of-the-art memory solution that delivers extremely high bandwidth. Frank Ferro will discuss the design and implementation considerations of GDDR6 memory subsystems to address the bandwidth needs of these next-generation inferencing engines.

11:15am – 12:00pm

Accelerating Data Interconnects with PCI Express™ 6.0 & 5.0 Interface IP

Speaker: Arjun Bangre, Director of Product Marketing, Interface IP, Rambus
Abstract: The latest generation of the PCI Express, PCIe™ 6.0, advances performance to 64 GT/s in support of advanced workloads and networking. In this presentation, interface technology expert, Arjun Bangre will discuss the changes implemented in PCI Express 6.0, such as PAM4 signaling and low-latency forward error correction (FEC). In addition, Arjun Bangre will contrast PCIe 6.0 and 5.0 and explain how Rambus can support the PCIe interface your next design requires.

12:15pm – 1:00pm

Memory Bandwidth for AI/ML Races Higher with HBM3

Speaker: Frank Ferro, Senior Director of Product Management, Rambus Interface IP
Abstract: With the insatiable need for higher bandwidth in state-of-the-art AI/ML training and HPC, the HBM standard has been on a rapid pace of improvement. The newly standardized HBM3 generation doubles the data rate to 6.4 Gb/s that offers up to 819 GB/s of memory bandwidth between an accelerator and a single HBM3 DRAM device. Memory interface technology expert, Frank Ferro will discuss how the Rambus 8.4 Gb/s HBM3 Memory Subsystem can provide the headroom and scalability needed for implementing state-of-the-art HBM designs.

2:00pm – 2:45pm

Implementing CXL™ 2.0 Interconnect Solutions

Speaker: Arjun Bangre, Director of Product Marketing, Interface IP, Rambus
Abstract: Compute Express Link™ (CXL) has evolved rapidly since its launch in 2019 and is slated for debut in the next generation of server platforms coming later this year. While it builds on the same physical layer as PCI Express, CXL implements unique features at the controller level to enable memory cache coherency between a host and multiple types of connected devices including smart NICs, accelerators and memory expansion devices. Join technology expert Arjun Bangre for a discussion of key features and implementation details for CXL interconnects.

3:00pm – 3:45pm

Securing Automotive Semiconductors in the New Centralized Car Architecture

Speaker: Thierry Kouthon, Product Manager, Security IP, Rambus
Abstract: Modern automobiles contain up to 100 Electronic Control Units (ECUs) or more. Particularly with the increasing adoption of Advanced Driver Assistance Systems (ADAS), cars are data centers on wheels. Cybersecurity is a growing imperative given widely publicized spectacular exploits and threats to both life and property. The automotive industry has identified Hardware Security Modules (HSM) embedded in ECUs as a viable and effective way to address automotive cybersecurity. Thierry Kouthon will discuss how ASIL-B/D and FIPS-certified root of trust solutions can be implemented as embedded HSMs in automotive chips.

4:00pm – 4:45pm

2.5D/3D Architecture Solutions

Speaker: Ming Li, Technical Director, Rambus
Abstract: 2.5D/3D solutions promise benefits including continued performance scaling and higher bandwidth connections between chips. In order to realize these benefits, expertise in power integrity (PI), signal integrity (SI), interposer design and system-level simulation are required. This presentation will cover the design considerations and methodologies for successfully implementing a 2.5D/3D design for an HBM2E/HBM3 system.

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