Visit us in booth #1035 to see our comprehensive suite of GDDR, SerDes and HBM IP Cores, and MACsec/IPsec Protocol Engines for today’s most challenging data center and networking applications. More information about our demos here.
We will also be hosting a full-day sponsored training session on Wednesday, January 29th.
Come hear our experts in a series of technical training sessions focusing on critical topics including: interface solutions for 5G; chiplet architecture interface alternatives; memory solutions for AI/ML; interface solutions for enterprise and hyperscale data centers; emerging requirements for automotive interfaces; 3D packaging solutions.
Session details below.
9:05 – 9:45 AM | Great America 3
Suresh Andani, Senior Director of Product Marketing, Rambus
5G, unlike previous generations of cellular networking technology, is truly revolutionary in its vision to enable an unprecedented number of use cases such as connected vehicles, high user-density at special events (Olympics), massive IoT (SmartCity, industrial), ultra-reliable low-latency applications (factory automation, healthcare). Data bandwidth, latency, and reliability requirements will be pushed to their limits necessitating an end-to-end transformation in the 5G Radio Access Network (RAN). Front-haul transport is moving from CPRI to Ethernet-based eCPRI, and dedicated base stations are being virtualized with adoption of Cloud RAN architecture. This session will cover the evolving physical interface solutions that are key to enabling this massive transformation.
11:05 – 11:45 AM | Great America 3
Saman Sadr, Vice President of Product Marketing for IP Cores, Rambus
As data grows at an accelerating pace, more compute power and bandwidth are required to process this data, driving the need for larger and more complex system on chips (SoCs). This is particularly true at a time when the benefits of scaling have slowed or stopped altogether. Further, as the complexity of SOCs increases, so do the costs to manufacture in leading-edge FinFET geometries. Chip disaggregation, or chiplets, offers an alternative to the traditional monolithic SoC scaling approach. Aggregating multiple chiplets to perform the function of a single monolithic IC de-risks the overall system by reducing complexity and increasing yields. This session will cover the architectures and interface alternatives critical for chiplet implementations.
12:05 – 12:45 PM | Great America 3
Frank Ferro, Senior Director of Product Marketing, Rambus
Rapid advances in artificial intelligence have re-energized the semiconductor industry, with numerous companies developing AI-specific silicon aimed at providing ever-higher levels of performance and power efficiency. As our increasingly connected world evolves, AI continues to evolve as well. But several critical challenges await chip and system designers as our industry strives to meet the relentless demands for more performance and better power efficiency. Among the most critical of these challenges are memory system bottlenecks impacting processor design. In this presentation we’ll cover the memory solutions, such as HBM2 and GDDR6, that can provide continued progress of AI silicon.
2:00 – 2:40 PM | Great America 3
Suresh Andani, Senior Director, Product Marketing, Rambus
Cloud-based workloads are driving continued evolution in enterprise and hyperscale data centers. Critical to the successful scaling of computing and networking devices are high-speed SerDes interfaces providing high-bandwidth communications between ASICs and SoCs. This presentation will cover the SerDes solutions such as PCIe 5, CXL and CCIX that are driving new levels of performance.
2:50 – 3:30 PM | Great America 3
Frank Ferro, Senior Director of Product Marketing, Rambus
Powering past 1GB per second of data generation is a breeze for the connected cars coming down the road. Infotainment, ADAS, sensor systems, communications and more demand the ability to handle a flood of real-time data. Learn about the memory and interface solutions able to move this torrent of data how to support the stringent manufacturing and functional safety requirements of the automotive market.
3:45 – 4:25 PM | Great America 3
Ming Li, Technical Director, Rambus
3D packaging promises benefits including continued performance scaling and higher bandwidth connections between chips. In order to realize these benefits expertise in power integrity (PI), signal integrity (SI), interposer design and system-level simulation are required. This presentation will cover the design considerations and methodologies for successfully implementing a 3D package design for an HBM2/HBM2E solution.
Stop by and see 112G LR PHY demonstration of a comprehensive IP solution designed to provide best-in-class performance across challenging long-reach signaling environments for next-generation networks and hyper-scale data centers. It supports PAM-4 and NRZ signaling and data rates from 10.31 to 106.25 Gbps across copper and backplane channels with more than 35dB insertion loss.
We will be showing our HBM2 memory interface, consisting of PHY and Northwest Logic memory controller, demonstrating error free, high margin continuous read and write to memory. This HBM2 memory interface is designed for a 2.5D interposer system design and supports a total bandwidth up to 256 GB/s.
Learn how MACsec and IPsec protocol engines can secure, without altering, network traffic. Rambus offers complete inline solutions that seamlessly integrate with your network interface and look-aside engines. These offload system CPUs and accelerate L3/L4 security protocols, Linux crypto APIs and more.
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