Rambus @ DesignCon 2023

Join Rambus for a day of technical sessions at DesignCon on February 1, 2023.

Hear from our experts on the technologies that are set to shape the future of data centers and high-performance systems, and discover how our cutting-edge memory, interconnect and security IP enables today’s most challenging computing, edge, automotive and IoT applications. All sessions will be held in Great America 1.

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Technical Training Agenda

TimeSession Information
8:00am – 8:45am

Technologies that will Shape the Future of the Data Center

Speaker: Steven Woo, Fellow and Distinguished Inventor, Rambus
Abstract: Server and data center architectures are rapidly evolving in response to the growing volume and importance of digital data. The meteoric rise of AI/ML and advanced workloads accelerate this change. New memory and interconnect technologies are key to tackling a growing list of challenges that architects must address to meet the needs for future data centers.

9:00am – 9:45am

Choosing the Right High-Performance Memory Solution

Speaker: Frank Ferro, Senior Director of Product Management, Interface IP, Rambus
Abstract: Demanding workloads such as AI/ML training, network graphics and HPC have led to the development of application-specific silicon. To keep these processors and accelerators fed requires state-of-the-art memory solutions that deliver extremely high bandwidth. Performance, design and implementation considerations need be examined in selecting the right memory for next-generation computing applications.

11:15am – 12:00pmAutomotive IP Solutions for the Software-Defined Vehicle

: Lou Ternullo, Senior Director of Product Marketing, Interface IP, Rambus; Thierry Kouthon, Principal Engineer, Product Management, Security IP, Rambus; Justin Endo, Senior Manager, Marketing & Sales, Mixel
Abstract: Automotive systems, and the semiconductors used within them, are some of the most complex electronics seen today. That complexity is set to dramatically rise as cars reach new levels of automation. This panel will explore some of the main technical and certification challenges facing automotive designers and discuss how IP solutions can help meet demanding performance, safety and security requirements.
12:15pm – 1:00pm

Memory Encryption Solutions for Protecting Data in Use

Speaker: Scott Best, Senior Director, Security IP, Rambus
Abstract: There are many challenges to achieving good “memory security,” especially in that the term “memory” could refer to on-chip SRAM, embedded non-volatile memory, or even off-chip memory (e.g., both DRAM or mass-storage non-volatile). We refer to data within non-executable NVM to be “data at rest,” while data within volatile memory like SRAM or DRAM to be “data in use.” In both domains, data within these memories is of interest to an adversary – it has either immediate value (e.g., passwords, secret keys, AI/ML datasets, etc.), or it can indirectly lead to exposure of those valuable assets. This presentation will focus on the key aspects of memory security for data-in-use applications: 1) data privacy, 2) data authenticity, and 3) data freshness, and how those security aspects weigh against critical performance metrics including latency and memory overhead.

2:00pm – 2:45pm

Accelerating Data Interconnects with PCI Express 6.0 Interface IP

Speakers: Lou Ternullo, Senior Director of Product Marketing, Interface IP, Rambus
Abstract: The latest generation of PCI Express® (PCIe®) 6.0, advances performance to 64 GT/s in support of advanced data center workloads and networking. In this presentation, interface technology experts, Robert Wang and Lou Ternullo will discuss the new features implemented in PCIe 6.0, such as PAM4 signaling and low-latency forward error correction (FEC). They will also show how Rambus PCIe interface IP can support your future design requirements.

3:00pm – 3:45pm

CXL Advances Data Center Performance with Memory Tiering Architecture

Speakers: Danny Moore, Senior Product Marketing Manager, CXL Processing Solutions, Rambus
Abstract: CXL™ technology promises tremendous gains in computing performance by bridging the latency gap between direct-attached DRAM main memory and solid-state storage. Rambus CXL experts will discuss the market requirements and technology challenges addressed by memory tiering. Memory tiering solutions, and their many possible deployments, as well as software orchestration and management of tiered-memory architectures will be discussed.

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