We’re excited to participating in the 2025 Andes RISC-V Con Beijing! Stop by and chat with our team about our Silicon IP offerings.
Xinyu Jiang, Director of Business Development at Rambus, will also be giving a presentation titled “How to improve the security level of RISC-V based SoC designs with RISC-V based root of trust. Session information and abstract below.
To register and learn more about the event, follow the link here: https://www.andestech.com/Andes_RISC-V_CON_2025_CN/
How to improve the security level of RISC-V-based SoC designs with RISC-V-based root of trust
Xinyu Jiang, Director of Business Development, Rambus Asia Pacific
Time: 11:55-12:10
In this talk, Rambus will provide an overview of how the general-purpose RISC-V architecture can extend the computing subsystem of the general-purpose RISC-V architecture by integrating a RISC-V-based Root-of-Trust or Hardware Security Module (HSM) to provide security and cryptographic services to the platform. The root of trust enables a hardware-enforced trusted execution environment that supports trusted and secure identity, lifecycle and configuration management, secure boot and firmware management, secure debugging, and more.
For specific areas, such as automotive applications, additional functional safety mechanisms are required; Data centers and other fields have higher requirements for side-channel attack (SCA) protection capabilities. To achieve a future-proof security architecture, a new generation of quantum-resistant cryptographic accelerators can be introduced.
Rambus will demonstrate how to integrate physical interfaces, secure firmware, and middleware stack components at the hardware RTL level, and finally introduce safety and functional safety-related authentication systems and compliance guidance.
