Join us for OCP Global Summit in October! Larrie Carr, VP of Engineering, and Danny Moore, Sr. Manager of Data Center Solutions, will be speaking on exciting topics such as hotness tracking in hardware, memory scalability in AI, composable memory systems using CXL, polymorphic architecture, and error and corruption mitigation in data centers. Check out session details and abstracts below.
To register and learn more about the 2023 OCP Global Summit, follow the link here: https://www.opencompute.org/summit/global-summit
Title: Hotness Tracking in Composable Memory Systems
Track: Server: Composable Memory Systems
When: Wed, October 18, 12:50pm – 1:10pm | SJCC – Concourse Level – 220B
Abstract: Composable Memory Systems project considers all the system aspects of using tiered memory solutions to address the increasing capacity and performance needs of next generations servers. AI/ML systems, Virtualized servers and large memory systems have driven demand for such solutions. New interconnects (e.g. CXL) show significant promise to bring such systems to reality. To achieve effective tiering of memory, there is a need to understand application usage in real time. This presentation will discuss proposals for hotness tracking in hardware that will enable HW/SW co-design in Composable Memory Systems.
Speakers: Samir Rajadnya, Principal Architect – Microsoft; Durgesh Srivastava, Senior Director – NVIDIA; Larrie Carr, VP Engineering – Rambus
Title: Memory Scalability in AI Co-design
Track: AI Hardware – Software Codesign
When: Wed, October 18, 3:50pm – 4:05pm | SJCC – Lower Level – LL20BC
Speaker: Danny Moore, Sr. Manager of Data Center Solutions – Rambus
Title: Panel: Composable Memory Systems using CXL
Track: Server: Composable Memory Systems
When: Wed, October 18, 3:50pm – 4:35pm | SJCC – Concourse Level – 220B
Abstract: AI/ML, Cache, Database, Data Warehouse and Virtualized servers are driving the need for higher memory capacity and bandwidth. The current memory hierarchy and solutions are limited to CPU-attached memory. However, CXL now opens up new potential “Composable Memory Systems” in the next generation data center solutions. First, we have the potential to dramatically increase memory capacities in some platforms using memory expansion. Second, we can now build TCO-optimized memory tiers. This requires the industry to come together to develop HW/SW co-designed OCP solutions. Panelists will discuss their plans to enable Composable Memory Systems via OCP CMS sub-project initiatives to deliver TCO-optimized memory solutions.
Title: Panel: Polymorphic Architecture Meets Large AI Models
Track: AI Hardware – Software Codesign
When: Wed, October 18, 4:10pm – 5:00pm | SJCC – Lower Level – LL20BC
Speakers: Brian Hirano, Director – Micron; Vijay Janapa Reddi, Associate Professor – Harvard University, Weifeng Zhang, Chief Architect & VP of Software – Lightelligence; Allan Cantle, CEO – Nallasway; Danny Moore, Sr. Manager of Data Center Solutions – Rambus; Tushar Krishna, Associate Professor – Georgia Institute of Tech
Title: Mitigating Silent Errors and Corruption within the Data Center
Track: Server: Composable Memory Systems
When: Wed, October 18, 4:35pm – 5:00pm | SJCC – Concourse Level – 220B
Abstract: The introduction of CXL has enabled a new class of SoC solutions within the data center server beyond the traditional CPU and DRAM devices. While the industry struggles with silent data corruption and error execution problems with the current server designs, these new SoC devices could significantly affect data center stability unless they also adopt architecture, design and production techniques to maximize their data integrity performance. This presentation will review the sources of data integrity problems and the methods developed for the storage and automotive markets may be applied to the new class of CXL silicon products.
Speaker: Anjaneya “Reddy” Chagam – Cloud Architect; Manoj Wadekar, Hardware Systems Technologist – Meta; Siamak Tavallaei, Chief Systems Architect – Independent; Larrie Carr, VP Engineering – Rambus; Sandeep Dattaprasad, Sr. Product Manager – Astera Labs; Samir Rajadnya, Principal Architect – Microsoft
Title: Introduction to CXL Fabrics
Track: Server: Hardware Management with DC-SCM
When: Thu, October 19, 12:50pm – 1:10pm | SJCC – Lower Level – 20BC
Abstract: This session will introduce CXL Fabrics, a new multi-level switch architecture introduced in CXL 3.0. CXL Fabrics are not restricted to tree-based topologies and can scale to 4,096 nodes, offering substantial scale and flexibility. The presentation will cover the transport level details, routing model, and management architecture.
Speaker: Vincent Hache, Director of Systems Engineering – Rambus
