Interface IP chip icon

Interface IP

Memory Controllers

Silicon-proven, high-performance Northwest Logic memory controller cores are optimized for use in SoCs, ASICs and FPGAs. These market leading solutions for memory interfaces address AI, automotive, data center, network edge, IoT and mobile applications.

ProductProduct BriefProtocolApplication
GDDR6 ControllerDownload GDDR6 Controller Product Brief GDDR6AI, Automotive, Graphics
HBM2E ControllerDownload HBM2 Controller Product Brief HBM2, HBM2EAI, Data Center, Graphics
LPDDR4 ControllerDownload LPDDR4 Controller Product BriefLPDDR4Mobile, IoT, Automotive
DDR4 ControllerDownload DDR4 Controller Product BriefDDR4Data Center, Edge
DDR3 ControllerDownload DDR3 Controller Product BriefDDR3IoT, Edge
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Standards Compatible

Faster time-to-market

Fully verified

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Flexible Design

Full programmability

Customization options

Reduced Power

Power optimized

Minimum gate count

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Improved Performance

Industry-leading data rates

High memory throughput

Rambus offers a full range of Northwest Logic memory controllers and add-on cores
Rambus offers a full range of Northwest Logic memory controllers and add-on cores
Download HBM2 and GDDR6: Memory Solutions for AI white paper

HBM2E and GDDR6: Memory Solutions for AI

Artificial Intelligence/Machine Learning (AI/ML) growth proceeds at a lightning pace. In the past eight years, AI training capabilities have jumped by a factor of 300,000 driving rapid improvements in every aspect of computing hardware and software. Meanwhile, AI inference is being deployed across the network edge and in a broad spectrum of IoT devices including in automotive/ADAS. Training and inference have unique feature requirements that can be served by tailored memory solutions. Learn how HBM2E and GDDR6 provide the high performance demanded by the next wave of AI applications.
2.5D/3D Packaging Solutions for AI and HPC

2.5D/3D Packaging Solutions for AI and HPC

For AI and HPC applications, HBM2E memory can deliver excellent bandwidth, capacity and latency in a very compact footprint thanks to its 2.5D/3D structure. The flipside is that this same structure leads to greater design complexity and raises a new set of implementation considerations.

Upcoming Webinar: AI Requires Tailored DRAM Solutions