The Rambus DDR3 memory PHY is fully compatible with DDR3 at 1.5V and DDR3L at 1.35V and scalable to 2133Mbps. The PHY has undergone extensive design-phase modeling and simulation of alternative SOC, package and PCB environments to ease implementation and enable first-time-right designs.
The Northwest Logic DDR3 controller maximizes memory bus efficiency via Look-Ahead command processing, bank management, auto-precharge and additive latency support. The core is DFI compatible and supports a range of interfaces to user logic.
The Rambus DDR3 PHY and Northwest Logic DDR3 controller used together comprise a complete DDR3 memory interface subsystem. Alternatively, these cores can be licensed separately to be paired with 3rd-party DDR3 controller or PHY solutions.
Engineering Design Services:
|Protocol||Data Rate (Mbps) Max.||Application|
|DDR3||800 to 2133||IoT, Edge|
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