Interface IP chip icon

Interface IP

DDR3 Controller

The Northwest Logic DDR3 controller core is designed for high memory throughput, high clock rates, and full programmability in computing and networking applications.  With the Rambus DDR3 PHY it comprises a complete DDR3 memory interface subsystem.

How the DDR3 Interface works

The Northwest Logic DDR3 controller maximizes memory bus efficiency via Look-Ahead command processing, bank management, auto-precharge and additive latency support. The core is DFI compatible and supports a range of interfaces to user logic.

The Rambus DDR3 memory PHY is fully compatible with DDR3 at 1.5V and DDR3L at 1.35V and scalable to 2133Mbps. The PHY has undergone extensive design-phase modeling and simulation of alternative SOC, package and PCB environments to ease implementation and enable first-time-right designs.

DDR3 Memory Interface Subsystem
DDR3 Memory Interface Subsystem

The Rambus DDR3 PHY and Northwest Logic DDR3 controller used together comprise a complete DDR3 memory interface subsystem. Alternatively, these cores can be licensed separately to be paired with 3rd-party DDR3 controller or PHY solutions.

Data Center to End Device: AI/ML Inferencing with GDDR6 cover

From Data Center to End Device: AI/ML Inferencing with GDDR6

Created to support 3D gaming on consoles and PCs, GDDR packs performance that makes it an ideal solution for AI/ML inferencing. As inferencing migrates from the heart of the data center to the network edge, and ultimately to a broad range of AI-powered IoT devices, GDDR memory’s combination of high bandwidth, low latency, power efficiency and suitability for high-volume applications will be increasingly important. The latest iteration of the standard, GDDR6 memory, pushes data rates to 18 gigabits per second and device bandwidths to 72 gigabytes per second.

Solution Offerings

Protocol Compatibility

ProtocolData Rate (Mbps) Max. Application
DDR3800 to 2133IoT, Edge