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Interface IP

DDR3 Controller

The Northwest Logic DDR3 controller core is designed for high memory throughput, high clock rates, and full programmability in computing and networking applications.  With the Rambus DDR3 PHY it comprises a complete DDR3 memory interface subsystem.

How the DDR3 Interface works

The Rambus DDR3 memory PHY is fully compatible with DDR3 at 1.5V and DDR3L at 1.35V and scalable to 2133Mbps. The PHY has undergone extensive design-phase modeling and simulation of alternative SOC, package and PCB environments to ease implementation and enable first-time-right designs.

The Northwest Logic DDR3 controller maximizes memory bus efficiency via Look-Ahead command processing, bank management, auto-precharge and additive latency support. The core is DFI compatible and supports a range of interfaces to user logic.

DDR3 Memory Interface Subsystem
DDR3 Memory Interface Subsystem

The Rambus DDR3 PHY and Northwest Logic DDR3 controller used together comprise a complete DDR3 memory interface subsystem. Alternatively, these cores can be licensed separately to be paired with 3rd-party DDR3 controller or PHY solutions.

Hidden Signals: The Memories and Interfaces Enabling IoT, 5G, and AI

This IDC Technology Spotlight Report, sponsored by Rambus, highlights key, often hidden, memory and interface technologies that are enabling high performance electronic systems to serve the disruptive trends of the next decade like IoT, 5G, and Artificial Intelligence.

Solution Offerings

  • Maximizes bus efficiency via look-ahead command processing, bank management, auto-precharge and additive latency support
  • Latency minimized via parameterized pipelining
  • Achieves high clock rates with minimal routing constraints
  • Supports full-rate and half-rate clock operation
  • Multi-mode controller support
  • Full run-time configurable timing parameters and memory settings
  • Supports ODT, dynamic ODT, 2T timing and write leveling calibration
  • DFI compatible
  • Full set of Add-On cores available
  • Minimal ASIC gate count
  • Broad range of ASIC and FPGA platforms supported
  • Delivered fully integrated and verified with target PHY
  • Core (source code)
  • Testbench (source code)
  • Complete documentation
  • Expert technical support
  • Maintenance updates

Engineering Design Services:

  • Customization
  • SoC integration

Protocol Compatibility

ProtocolData Rate (Mbps) Max. Application
DDR3800 to 2133IoT, Edge

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