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Interface IP

GDDR6 Controller

The Northwest Logic GDDR6 controller core is designed for use in applications requiring high memory throughput including graphics, advanced driver assistance systems (ADAS), data center and artificial intelligence (AI). With the Rambus GDDR6 PHY it comprises a complete GDDR6 memory interface subsystem.

How the GDDR6 Interface works

Originally designed for graphics applications, GDDR6 is a high-performance memory solution that can be used in a variety of compute-intensive applications.

The Rambus GDDR6 PHY is fully compliant to the JEDEC GDDR6 (JESD250) standard, supporting up to 18 Gbps per pin. The GDDR6 interface supports 2 channels, each with 16 bits for a total data width of 32 bits. At 18 Gbps per pin, the Rambus GDDR6 PHY offers a bandwidth of 72 GB/s. The PHY is available in advanced FinFET nodes for leading-edge SoC integration. Rambus works directly with customers to provide full-system signal and power integrity analysis, creating an optimized chip layout. Customers receive a hard macro solution with a full suite of test software for quick turn-on, characterization and debug.

GDDR6 Memory Interface Subsystem
GDDR6 Memory Interface Subsystem

The Northwest Logic GDDR6 controller fully supports the bandwidth and dual channel capabilities of the Rambus GDDR6 PHY. It maximizes memory bandwidth and minimizes latency via Look-Ahead command processing. The core is DFI compatible (with extensions for GDDR6) and supports AXI, OCP or native interface to user logic.

The Rambus GDDR6 PHY and Northwest Logic GDDR6 controller used together comprise a complete GDDR6 memory interface subsystem. Alternatively, these cores can be licensed separately to be paired with 3rd-party GDDR6 controller or PHY solutions.

Download HBM2 and GDDR6: Memory Solutions for AI white paper

HBM2E and GDDR6: Memory Solutions for AI

Artificial Intelligence/Machine Learning (AI/ML) growth proceeds at a lightning pace. In the past eight years, AI training capabilities have jumped by a factor of 300,000 driving rapid improvements in every aspect of computing hardware and software. Meanwhile, AI inference is being deployed across the network edge and in a broad spectrum of IoT devices including in automotive/ADAS. Training and inference have unique feature requirements that can be served by tailored memory solutions. Learn how HBM2E and GDDR6 provide the high performance demanded by the next wave of AI applications.

Solution Offerings

  • Supports up to 20 Gbps per pin operation
  • Can handle two x16 GDDR6 channels with one controller or independently with two controllers
  • Supports x8 or x16 clamshell mode
  • Queue-based interface optimizes performance and throughput
  • Maximizes memory bandwidth and minimizes latency via Look-Ahead command processing
  • Automatic retry on transactions where EDC error detected
  • Full run-time configurable timing parameters and memory settings
  • Supports automatic and controller-initiated training
  • DFI compatible (with extensions for GDDR6)
  • Full set of Add-On cores available including in-line ECC core
  • Supports AXI, OCP or native interface to user logic
  • Delivered fully integrated and verified with target GDDR6 PHY
  • Core (source code)
  • Testbench (source code)
  • Complete documentation
  • Expert technical support
  • Maintenance updates

Engineering Design Services:

  • Customization
  • SoC integration

Protocol Compatibility

ProtocolData Rate (Gbps) Max. Application
GDDR620AI, Data Center, Graphics
The Rambus GDDR6 PHY IP Core thumbnail

The Rambus GDDR6 PHY IP Core

The JEDEC-compliant Rambus GDDR6 PHY IP Core is optimized for systems that require low-latency and high-bandwidth GDDR6 memory solutions. Available on leading FinFET process nodes, the PHY interface supports two independent channels, with each supporting 16 bits for a total data width of 32 bits. In addition, the PHY supports speeds up to 16Gbps per pin, providing a maximum bandwidth of up to 64 GB/s.

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