Interface IP
LPDDR5 Controller
The Rambus LPDDR5 controller core is designed for use in applications requiring high memory throughput at low power including mobile, automotive, Internet of Things (IoT), laptop PCs, and edge networking devices.
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Product BriefHow the LPDDR5 Controller works
The LPDDR5 controller core accepts commands using a simple local interface and translates them to the command sequences required by LPDDR5 devices. The core also performs all initialization, refresh and power-down functions.
The core uses bank management logic to monitor the status of each LPDDR bank. Banks are only opened or closed when necessary, minimizing access delays.
The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges further improving overall throughput.
Add-On Cores such as an AXI Core Bus Interface, Multi-Port Front-End and In-Line ECC Core can be optionally delivered with the core. The core is delivered fully integrated and verified with the target LPDDR5 PHY.
Data Center Evolution: Accelerating Computing with PCI Express 5.0
The PCI Express® (PCIe) interface is the critical backbone that moves data at high bandwidth between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. The rise of cloud-based computing and hyperscale data centers, along with high-bandwidth applications like artificial intelligence (AI) and machine learning (ML), require the new level of performance of PCI Express 5.0.
Solution Offerings
- Support for LPDDR5 devices as described in the JEDEC JESD209-5A LPDDR5 DRAM Specification
- Bank management logic monitors status of each bank
- Queue based user interface with reordering scheduler
- Look-ahead Activate, Precharge, and Auto-Precharge logic
- Parity protection for all stored control registers
- PHY interface based on DFI 5.0 standard
- Each controller instance supports a single channel
- Supports Multiple Ranks (typically 2 or 4)
- Supports WCK:CK Ratio 4:1
- Supports x16 mode
- Supports Burst Length BL16 and BL32
- Supports data bus inversion (DBI) feature (read and/or write)
- Supports Masked Write (MWR)
- Supports mode register write (MRW) and mode register read (MRR) functions
- Supports Background ZQ Calibration mode and Command based ZQ Calibration mode
- Supports LPDDR5 speeds up to 6.4 Gbps/pin (800MHz controller clock)
- Supports all defined LPDDR5 channel densities (up to and including 32 Gb per LPDDR5 channel)
- Supports LPDDR5 Bank architecture BG mode and 16B mode
- Supports LPDDR5 per-bank refresh and all-bank refresh
- Supports LPDDR5 Refresh Management
- Supports LPDDR5 device Self-Refresh mode
- Supports LPDDR5 device Power-Down mode
- Automatic generation of initialization and refresh sequences
- Built-in Activity Monitor
- Optional multi-burst capability
- Full set of Add-On cores available
- Delivered fully integrated and verified with target LPDDR PHY
- Customization and integration services available
- Core (source code)
- Testbench (source code)
- Complete documentation
- Complete documentation
- Maintenance updates
- Customization
- SoC integration
Protocol Compatibility
| Protocol | Data Rate (Gbps) | Application |
|---|---|---|
| LPDDR5 | 6.4 | Mobile, Automotive, IoT |
Resources
Videos
CSI – DSI Demonstration (Rambus MIPI Fidus Inrevium FMC)