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Interface IP

LPDDR5 Controller

The Rambus LPDDR5 controller core is designed for use in applications requiring high memory throughput at low power including mobile, automotive, Internet of Things (IoT), laptop PCs, and edge networking devices.

How the LPDDR5 Controller works

The LPDDR5 controller core accepts commands using a simple local interface and translates them to the command sequences required by LPDDR5 devices. The core also performs all initialization, refresh and power-down functions.

The core uses bank management logic to monitor the status of each LPDDR bank. Banks are only opened or closed when necessary, minimizing access delays.

The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges further improving overall throughput.

LPDDR5 Memory Interface Subsystem Block Diagram
LPDDR5 Memory Interface Subsystem Block Diagram

Add-On Cores such as an AXI Core Bus Interface, Multi-Port Front-End and In-Line ECC Core can be optionally delivered with the core. The core is delivered fully integrated and verified with the target LPDDR5 PHY.

Data Center Evolution: Accelerating Computing with PCI Express 5.0

Data Center Evolution: Accelerating Computing with PCI Express 5.0

The PCI Express® (PCIe) interface is the critical backbone that moves data at high bandwidth between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. The rise of cloud-based computing and hyperscale data centers, along with high-bandwidth applications like artificial intelligence (AI) and machine learning (ML), require the new level of performance of PCI Express 5.0. 

Solution Offerings

Protocol Compatibility

ProtocolData Rate (Gbps) Application
LPDDR56.4Mobile, Automotive, IoT