Interface IP
DSI-2 Controller Core
The Northwest Logic DSI-2 controller core is a second-generation MIPI DSI core optimized for high performance, low power and small size. The core is fully compliant with the DSI-2 standard and implements all three layers defined therein: Pixel to Byte Packing, Low Level Protocol, and Lane Management.
Contact
Product Brief
MIPI Drives Performance for Next-Generation Displays
Download this white paper to learn how MIPI DSI-2 interface and VESA® DSC visually lossless compression technologies can meet the challenges of next-generation displays.Solution Offerings
Features
- Fully DSI-2/DSI standard compliant
- 64 and 32-bit core widths
- Host (Tx) and Peripheral (Rx) versions
- Supports 1-4, 2.5+ Gbps D-PHY data lanes
- Supports 1-4, 2.5+ Gsym/s C-PHY lane (trio)
- Supports all data types
- Easy-to-use native interface
- Delivered fully integrated and verified with target MIPI PHY
Deliverables
- Core (source code)
- Testbench (source code)
- Complete documentation
- Expert technical support
- Maintenance updates
Services
Engineering Design Services:
- Customization
- SoC integration
Next-Generation Displays: An Integrated IP Solution from Mixel, Rambus & Hardent
Displays for next-generation smartphones, AR/VR devices, and automotive systems all require more bandwidth than ever before. Using a combination of VESA Display Stream Compression (DSC) with the MIPI Display Serial Interface (DSI-2) technology, designers can achieve display resolutions up to 8K without compromise to video quality, battery life or cost.
Protocol Compatibility
| Protocol | Data Rate (Gbps) | Application |
|---|---|---|
| DSI-2/DSI | 2.5+ | Mobile, IoT |
Resources
Videos
CSI – DSI Demonstration (Rambus MIPI Fidus Inrevium FMC)