MIPI DSI-2 Controller Core

The Rambus MIPI DSI-2 controller core is optimized for high performance, low power and small size. The core is fully compliant with the DSI-2 standard and implements all three layers defined therein: Pixel to Byte Packing, Low Level Protocol, and Lane Management.

MIPI DSI-2 Controller Block Diagram (Host Version)
MIPI DSI-2 Controller Block Diagram (Host Version)

Leveraging VESA Video Compression & MIPI DSI-2 for High-Performance Displays

Watch Webinar

Visually lossless video compression is essential for handling the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths. This presentation will show designers how they can develop cutting-edge display products without compromising on display quality, battery life or cost using a combination of VESA video compression and MIPI DSI-2 technology.

Solution Offerings

Protocol Compatibility

ProtocolData Rate (Gbps) Application
DSI-2/DSI9.0+Mobile, IoT, Automotive
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