Interface IP
CXL and PCI Express Controllers
Silicon-proven, high-performance CXL and PCI Express (PCIe) controller cores are optimized for use in SoCs, ASICs and FPGAs. These market leading solutions for high-performance interfaces address AI/ML, data center and edge applications.
Contact| Product | Brief | Protocol | Application |
|---|---|---|---|
| CXL 2.0 Controller |  | CXL 2.0, 1.1 | Data Center, AI/ML, HPC |
| PCIe 6.0 Controller | | PCIe 6.0, 5.0, 4.0, 3.1/3.0 | Data Center, AI/ML, HPC |
| PCIe 6.0 Retimer Controller with CXL Support | | PCIe 6.0, 5.0, 4.0, 3.1/3.0, CXL 2.0 | Data Center, AI/ML, HPC |
| PCIe 5.0 Controller | | PCIe 5.0, 4.0, 3.1/3.0 | Data Center, AI/ML, HPC |
| PCIe 5.0 Multi-port Switch | | PCIe 5.0, 4.0, 3.1 | Data Center, AI/ML, HPC |
| PCIe 4.0 Controller | | PCIe 4.0, 3.1/3.0 | Data Center, Edge, Graphics |
| PCIe 3.1 Controller | | PCIe 3.1/3.0 | Data Center, Edge, Graphics |
| PCIe 2.1 Controller | | PCIe 2.1, 1.1 | Data Center, Edge, Graphics |
| CCIX 1.1 Controller | | CCIX 1.1 | Data Center, AI/ML, HPC |
| PCIe Controller for USB4 | | USB4/PCIe 5.0 | Computing |
| PCIe Switch for USB4 | | USB4/PCIe 5.0 | Computing |
| Many-Channel AXI DMA | | PCIe and others | Data Center |
| Debug and Test Solutions | PCIe 5.0, 4.0, 3.1 | Data Center, Computing |
Add-On Cores
Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.0
The PCIe interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the torrid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.0 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard.
Data Center Evolution: Accelerating Computing with PCI Express 5.0
The PCI Express® (PCIe) interface is the critical backbone that moves data at high bandwidth between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. The rise of cloud-based computing and hyperscale data centers, along with high-bandwidth applications like artificial intelligence (AI) and machine learning (ML), require the new level of performance of PCI Express 5.0.
Resources
Videos
Demonstration of a CXL Interconnect on a FPGA-based design