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Interface IP

PCIe 4.0 Digital Controller

The Northwest Logic Expresso 4.0 Digital Controller is designed to achieve maximum PCI Express (PCIe) 4.0 performance with great design flexibility and ease of integration. It is fully backward compatible with PCIe 3.0, 2.1 and 1.1. With the Rambus PCIe 4.0 PHY it forms a comprehensive interface solution delivering high-bandwidth and low-latency connectivity for demanding applications in data center, edge and graphics.

How the PCIe 4.0 Interface works

The Expresso 4.0 digital controller and PCIe 4.0 PHY together comprise a high-performance serial link subsystem. Optimized for challenging, performance-intensive applications, our PCIe 4.0 interface solution is ideal for data center, edge and graphics.

PCIe 4.0 Interface Subsystem Example
PCIe 4.0 Interface Subsystem Example

The Expresso 4.0 digital controller has been co-verified with the PCIe 4.0 PHY. Both PHY and controller support PCIe 4.0, 3.0 and 2.1 protocols and are PIPE 4.2 compliant. They can be used together or paired with PIPE 4.2-compliant 3rd-party solutions.

Data Center to End Device: AI/ML Inferencing with GDDR6 cover

From Data Center to End Device: AI/ML Inferencing with GDDR6

Created to support 3D gaming on consoles and PCs, GDDR packs performance that makes it an ideal solution for AI/ML inferencing. As inferencing migrates from the heart of the data center to the network edge, and ultimately to a broad range of AI-powered IoT devices, GDDR memory’s combination of high bandwidth, low latency, power efficiency and suitability for high-volume applications will be increasingly important. The latest iteration of the standard, GDDR6 memory, pushes data rates to 18 gigabits per second and device bandwidths to 72 gigabytes per second.

Solution Offerings

  • Complete SerDes subsystem solution with co-validated PCIe 4.0 PHY
  • PIPE 4.2-compliant interface for integration with 3rd-party PHYs
  • Supports PCIe 4.0, 3.0 and 2.1
  • Duplex lane configurations of x1, x2, x4, x8 and x16
  • 16, 8, 5 and 2.5 Gbps SerDes support
  • 1-8 Physical Function support
  • SR-IOV support with up to 255 Virtual Functions
  • Endpoint, Root Port, Upstream Switch Port, Downstream Switch Port, Bifurcation support
  • 32, 64, 128, 256-bit core width support
  • Flexible equalization algorithms
  • Transaction Layer (TL), Partial TL interface bypass options
  • AER, ECRC, MSI-X, MSI, Lane Reversal support, L1 PM substates, SRIS, ECC/Parity Protection
  • Fully validated with target PHY
  • Core (source code)
  • Testbench (source code)
  • Complete documentation
  • Expert technical support
  • Maintenance updates

Engineering Design Services:

  • Customization
  • SoC integration

Protocol Compatibility

ProtocolData Rate (Gbps)  Application
PCIe 2.15High-bandwidth peripheral and graphics
PCIe 3.08Servers, storage, networking devices
PCIe 4.016Servers, storage, networking devices