Interface IP
PCIe 4.0 Digital Controller
The Northwest Logic Expresso 4.0 Digital Controller is designed to achieve maximum PCI Express (PCIe) 4.0 performance with great design flexibility and ease of integration. It is fully backward compatible with PCIe 3.0, 2.1 and 1.1. With the Rambus PCIe 4.0 PHY it forms a comprehensive interface solution delivering high-bandwidth and low-latency connectivity for demanding applications in data center, edge and graphics.
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Product BriefHow the PCIe 4.0 Interface works
The Expresso 4.0 digital controller and PCIe 4.0 PHY together comprise a high-performance serial link subsystem. Optimized for challenging, performance-intensive applications, our PCIe 4.0 interface solution is ideal for data center, edge and graphics.
The Expresso 4.0 digital controller has been co-verified with the PCIe 4.0 PHY. Both PHY and controller support PCIe 4.0, 3.0 and 2.1 protocols and are PIPE 4.2 compliant. They can be used together or paired with PIPE 4.2-compliant 3rd-party solutions.
Going Beyond GPUs with GDDR6
Supported by Micron Technology, SK Hynix and Samsung, GDDR6 SGRAM will feature a maximum data transfer rate of 16 Gbps, along with an operating voltage of 1.35V. GDDR6 offers higher densities compared to previous-generation graphics memory. In addition, GDDR6 doubles the speed (12–16 Gb/s) of GDDR5 and provides more than 5X the 3.2 Gb/s speed of DDR4. Although initially targeted at game consoles and PC graphics, the latest iteration of GDDR is expected to be deployed across multiple verticals, with Micron specifically highlighting the data center and automotive sector.
Solution Offerings
- Complete SerDes subsystem solution with co-validated PCIe 4.0 PHY
- PIPE 4.2-compliant interface for integration with 3rd-party PHYs
- Supports PCIe 4.0, 3.0 and 2.1
- Duplex lane configurations of x1, x2, x4, x8 and x16
- 16, 8, 5 and 2.5 Gbps SerDes support
- 1-8 Physical Function support
- SR-IOV support with up to 255 Virtual Functions
- Endpoint, Root Port, Upstream Switch Port, Downstream Switch Port, Bifurcation support
- 32, 64, 128, 256-bit core width support
- Flexible equalization algorithms
- Transaction Layer (TL), Partial TL interface bypass options
- AER, ECRC, MSI-X, MSI, Lane Reversal support, L1 PM substates, SRIS, ECC/Parity Protection
- Fully validated with target PHY
- Core (source code)
- Testbench (source code)
- Complete documentation
- Expert technical support
- Maintenance updates
Engineering Design Services:
- Customization
- SoC integration
Protocol Compatibility
| Protocol | Data Rate (Gbps) | Application |
|---|---|---|
| PCIe 2.1 | 5 | High-bandwidth peripheral and graphics |
| PCIe 3.0 | 8 | Servers, storage, networking devices |
| PCIe 4.0 | 16 | Servers, storage, networking devices |
