PCIe 4.0 Controller

The PCIe 4.0 Controller (formerly XpressRICH) is designed to achieve maximum PCI Express® (PCIe®) 4.0 performance with great design flexibility and ease of integration. It is fully backward compatible with PCIe 3.1/3.0. A PCIe 4.0 Controller with AXI (formerly XpressRICH-AXI) is also available. The controller delivers high-bandwidth and low-latency connectivity for demanding applications in data center, edge and graphics.

How the PCIe 4.0 Controller works

The PCIe 4.0 Controller is configurable and scalable IP designed for ASIC and FPGA implementation. It supports the PCIe 4.0 and 3.1/3.0 specifications, as well as the PHY Interface for PCI Express (PIPE) specification. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models.

PCIe 4.0 Controller Block Diagram
PCIe 4.0 Controller Block Diagram
PCIe 4.0 Controller with AXI Block Diagram
PCIe 4.0 Controller with AXI Block Diagram

The PCIe 4.0 Controller is verified using multiple PCIe VIPs and test suites, and is silicon proven in hundreds of designs in production. Rambus integrates and validates the PCIe 4.0 Controller with the customer’s choice of 3rd-party PCIe 4.0 PHY.

Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.0

Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.0

The PCIe interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the torrid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.0 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard. 

Solution Offerings

Protocol Compatibility

Protocol Signaling Rate (GT/s) Application
PCIe 3.1/3.0 8 Servers, storage, networking devices
PCIe 4.0 16 Servers, storage, networking devices
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