At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
DDR3 PHY
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Product BriefHow the DDR3 Interface Subsystem works
The Rambus DDR3 memory PHY is fully compatible with DDR3 at 1.5V and DDR3L at 1.35V and scalable to 2133Mbps. The PHY has undergone extensive design-phase modeling and simulation of alternative SOC, package and PCB environments to ease implementation and enable first-time-right designs.
The DDR3 controller maximizes memory bus efficiency via Look-Ahead command processing, bank management, auto-precharge and additive latency support. The core is DFI compatible and supports a range of interfaces to user logic.
The Rambus DDR3 PHY and DDR3 controller used together comprise a complete DDR3 memory interface subsystem. Alternatively, these cores can be licensed separately to be paired with 3rd-party DDR3 controller or PHY solutions.
Solution Offerings
- PLL-based clocking with internal clock alignment to the parallel clock on the memory controller interface
- Autonomous initialization
- Support for multiple channel configurations from x16 through x72 per channel
- Support for multiple DRAM widths (x4, x8, x16, x32)
- Support for single channel, 1 to 4 ranks
- Excepteur sint occaecat cupidatat non proident,
- Selectable low-power operating states
- DFI 3.1 compliant for easy integration with memory controller
- Programmable output impedance and on-die termination
- ZQ calibration of output impedance and on-die calibration
- Utilizes standard 8-layer 6020 metal layer stack.
- Supports C4 flip-chip packaging options
- Register interface for state observation
- Test traffic generation and error checking for in-situ test
- LabStation™ software environment for system level bring-up, characterization, and validation
- Fully-characterized hard macro (GDSII):
- Complete design views:
- Gate-level and IO models
- Verification test benches
- Layout abstracts (.lef)
- Timing models (.lib)
- Memory controller reference design
- Full Documentation
- Integration Guidelines
- Package and PCB design guidelines
- ASIC/DFT manufacturing guidelines
- Test and Characterization user guide
- Verilog models
- CDL netlists *(.cdl)
- ATPG models
- GDSII layout
- DRC & LVS reports
Comprehensive Chip and System Design Reviews
- Kickoff/Program Review
- Floor plan Review
- Test/Characterization Plan Review
- Package Design Review
- Board Design Review
- Final Chip Integration Review
- Bring-up and Test Review
Engineering Design Services:
- Package design
- System board layout
- Statistically-based signal and power integrity analysis
Memory Systems for AI and Leading-Edge Applications
Thanks to rapid advancements in computing, neural networks are fueling tremendous growth in AI for a broad spectrum of applications. Learn about the memory architectures, and their relative advantages, at the heart of the AI revolution.Protocol Compatibility
| Protocol | Data Rate (Gbps) | Application |
|---|---|---|
| DDR3 (1.5V) | 1600-2133 | IoT, Edge |
| DDR3L (1.35V) | 1600-1866 | IoT, Edge |
Inventions
FlexPhase™ Timing Adjustment Circuits
FlexPhase per bit timing adjustment circuits deskew data and clock signals to improve signal integrity and simplify package and PCB system design.
Output Driver Calibration
Output driver calibration allows SoC designers to tune the output signaling to optimal levels in order to improve data rates and system voltage margin.
On Die Termination Calibration
ODT calibration enables higher data rates and superior DRAM device and module performance by establishing the optimal termination value to compensate for variations in process and operating conditions that degrade signal performance.
Resources
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