At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
GDDR6 PHY
Designed for performance and power efficiency, the GDDR6 PHY enables applications requiring high memory throughput including AI/ML, graphics and networking applications. The GDDR6 PHY is available in two versions: 24G and 16G. With the Rambus GDDR6 Controller it comprises a complete GDDR6 memory interface subsystem.
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24G GDDR6 PHYHow the 24G GDDR6 Memory Interface Subsystem works
Originally designed for graphics applications, GDDR6 is a high-performance memory solution that can be used in a variety of compute-intensive applications.
The Rambus GDDR6 PHY is fully compliant to the JEDEC GDDR6 (JESD250C) standard, supporting up to 24 Gb/s per pin. The GDDR6 interface supports 2 channels, each with 16 bits for a total data width of 32 bits. At 24 Gb/s per pin, the Rambus GDDR6 PHY offers a bandwidth of 96 GB/s. Rambus works directly with customers to provide full-system signal and power integrity analysis, creating an optimized chip layout. Customers receive a hard macro solution with a full suite of test software for quick turn-on, characterization and debug.
The Rambus GDDR6 controller fully supports the bandwidth and dual channel capabilities of the Rambus GDDR6 PHY. It maximizes memory bandwidth and minimizes latency via Look-Ahead command processing. The core is DFI compatible (with extensions for GDDR6) and supports AXI or native interface to user logic.
The Rambus GDDR6 PHY and GDDR6 controller used together comprise a complete GDDR6 memory interface subsystem. Alternatively, these cores can be licensed separately to be paired with 3rd-party GDDR6 controller or PHY solutions.
From Data Center to End Device: AI/ML Inference with GDDR6
Created to support 3D gaming on consoles and PCs, GDDR packs performance that makes it an ideal solution for AI/ML inference. As inference migrates from the heart of the data center to the network edge, and ultimately to a broad range of AI-powered IoT devices, GDDR memory’s combination of high bandwidth, low latency, power efficiency and suitability for high-volume applications will be increasingly important.
Solution Offerings
- JESD250 Compliant
- Flexible delivery of IP core: works with ASIC/ SoC layout requirements
- Data rate: up to 24 Gb/s
- 2 Channels @ 16 bits/channel
- Support for 2 x 16 Clamshell mode
- DFI 3.1 style interface for easy integration with memory controller
- Memory controller or PHY can be ASIC interface master (PHY independent mode)
- Selectable low-power operating states
- Programmable Driver/Termination impedance value
- Driver/Termination Impedance calibration
- In-built test support
- Register interface for state observation
- LabStation™ software environment for system level bring-up, characterization, and validation
- Fully-characterized hard macro (GDSII)
- Complete design views:
- Gate-level and IO models
- Layout abstracts (.lef)
- Timing models (.lib)
- Verilog Behavior model
- CDL netlists (.cdl)
- GDSII layout
- DRC & LVS reports
- Full documentation:
- Datasheet
- Package design guidelines
- ASIC/DFT manufacturing guidelines
- Test and characterization user guide
Comprehensive Chip and System Design Reviews
- Kickoff/Program Review
- Floor plan Review
- Test/Characterization Plan Review
- Package Design Review
- Board Design Review
- Final Chip Integration Review
- Bring-up and Test Review
Engineering Design Services:
- Package design
- System board layout
- Statistically-based signal and power integrity analysis
