At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
The Rambus PCIe 4.0 PHY with the PLDA PCIe 4.0 digital controller comprise a high-performance serial link subsystem. Optimized for power in challenging, high-loss channels, our PCIe 4.0 interface solution is ideal for performance-intensive data center, edge and graphics applications.
The PHY comes complete with a PMA hard macro that supports PCIe 4.0, 3.0, and 2.0 protocols and a physical coding sublayer (PCS) soft macro for PCIe that is PIPE 4.2 compliant. Integrated with the PLDA PCIe 4.0 digital controller, the PHY can also be paired with 3rd-party PIPE 4.2-compliant controllers.
The PHY has a minimal set of broadside control and are configurable in x2, x4 and x8 lane configurations. This gives the PHY improved flexibility and support for a wide range of applications. The PCIe 4.0 PHYs is rigorously tested through 3rd-party compliance testing and internal interoperability system testing.
In order to improve system margin and performance, our solution features transmit and receive equalization and full equalization adaptation. This ensures that data is recovered even in the presence of channel and system interference.
Our PCIe 4 SerDes PHY is available on TSMC, Global Foundry and Samsung process nodes.
|Protocol||Signaling Rate (GT/s)||Application|
|PCIe 2.0||4||High bandwidth peripherals and graphics cards|
|PCIe 3.0||8||Enterprise solutions and chip to chip connectivity|
|PCIe 4.0||16||Hyperscale data center and big data applications|