At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
PCIe 6.0 SerDes PHY
The Rambus PCI Express® (PCIe®) 6.0 PHY is a low-power, area-optimized, silicon IP core designed with a system-oriented approach to maximize flexibility and ease of integration. It delivers up to 64 GT/s signaling rates in performance-intensive applications for artificial intelligence (AI), data center, edge, networking, and HPC.
The PCIe 6.0 PHY can be combined with the Rambus PCIe 6.0 controller core to make a complete PCIe 6.0 interface subsystem.
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PCIe 6.0 PHYHow the PCIe 6.0 Interface Works
The Rambus 6.0 PHY IP consists of a Physical Media Attachment (PMA) designed with a minimal set of broadside controls and status pins, as well as a configurable Physical Coding Sublayer (PCS), to support a wide range of server, storage and networking applications. The PHY can be combined with the Rambus PCIe 6.0 digital controller to offer a fully integrated and validated interface subsystem.
The PHY is configurable in x1, x2, x4, x8 and x16 lane configurations with bifurcation support. This gives the PHY improved flexibility and support for a wide range of applications. Multi-tap transmitter and adaptive receiver equalization supports more than 36dB of channel insertion loss. The PHY also supports the latest version of the Compute Express Link™ (CXL™) specification, version 3.0, enabling new use models for data center architectures.
The PCIe 6 SerDes PHY is available on advanced process nodes.
Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.0
The PCIe interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the torrid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.0 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard.Solution Offerings
- Complete SerDes subsystem solution with Rambus PCIe 6.0 controller core
- PIPE 6.0-compliant interface for Rambus PCI Express 6.0 Controller
- Duplex lane configurations of x1, x2, x4, x8 and x16 with bifurcation support
- Multi-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
- DSP based receive equalizer with Feed-Forward and Decision Feedback Equalizer
- (FFE/DFE) capable of compensating more than 36dB of channel insertion loss across PVT
- Floating DFE tap capable of compensating for reflection up to 40UI
- Support for transmitter and receiver spread spectrum clocking (SSC) to meet FCC regulations for electro-magnetic interference (EMI)
- Expandable register interface enabling communication with multiple PMAs and PCS-BIST soft macros
- Built-in Self Test (BIST) with ATPG and AC/DC Boundary scan support
- Built-in per-channel PRBS-7, 9, 11, 15, 23, 31 and user-defined pattern generation and checking for standalone loopback testing
- In-situ real-time monitoring and receive data eye schmoo enabling PCIe RX margining feature
- Operation across a wide temperature range (-40 to 125C)
- Automatic calibration of key circuits to maximize performance and yields
- Verilog models
- LEF abstracts (.lef)
- Timing models (.lib)
- CDL netlists (.cdl)
- ATPG models
- IBIS-AMI models
- GDSII layout
- DRC & LVS reports
- Datasheet
- SoC integration guide
- Optional design integration and bring-up support services
Comprehensive Chip and System Design Reviews
- Kickoff/Program Review
- Floor Plan Review
- Test/Characterization Plan Review
- Package Design Review
- Board Design Review
- Final Chip Integration Review
- Bring-up and Test Review
Engineering Design Services:
- Package design
- System board layout
- Statistically-based signal and power integrity analysis
Protocol Compatibility
| Protocol | Signaling Rate (GT/s) | Application |
|---|---|---|
| PCIe 3.1/3.0 | 8 | Servers, storage, networking devices |
| PCIe 4.0 | 16 | Servers, storage, networking devices |
| PCIe 5.0 | 32 | AI, servers, storage, networking, 5G infrastructure |
| PCIe 6.0 | 64 | AI, servers, storage, networking, 5G infrastructure |
Data Center Evolution: Accelerating Computing with PCI Express 5.0
The PCI Express® (PCIe) interface is the critical backbone that moves data at high bandwidth between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. The rise of cloud-based computing and hyperscale data centers, along with high-bandwidth applications like artificial intelligence (AI) and machine learning (ML), require the new level of performance of PCI Express 5.0.Inventions
