Interface IP
112G XSR Multi-protocol SerDes PHY
A high-bandwidth, ultra-low power SerDes PHY solution for extremely short reach (XSR) 112G inter-die connections in system in package (SiP) devices serving next-generation networking and hyperscale data center applications.
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Product BriefHow the 112G XSR PHY works
The Rambus 112G XSR Multi-Protocol SerDes (MPS) PHY is a comprehensive IP solution designed to provide best-in-class performance for the high-bandwidth connections between die or chiplets in SiP devices. The 112G MPS PHY supports PAM-4 and NRZ signaling and data rates from 25 to 112 Gbps. It is tailored for the ultra-low power and area requirements of die-to-die interfaces.
The 112G XSR MPS PHY is designed with a system-oriented approach, maximizing flexibility in today’s most challenging system environments including specifically:
- Die-to-die (D2D) interfaces
- Die-to-optical engine (D2OE) interfaces
Available in advanced 7nm FinFET process.
Solution Offerings
- Supports up to 8 duplex lanes and data rates from 25 to 112 Gbps
- Ultra-low power configurable architecture for D2D and D2OE interfaces
- Design flexibility allows for placement along all ASIC edges in an ASIC
- Programmable TX/RX equalizers including: Multi-tap digital FFE and CTLE
- A centralized LC-PLL supports a wide range of reference clock frequencies and lane operating frequencies
- PMA is spec. compliant across a wide operating junction temperature range (-20 °C to 105 °C). PLLs, bias circuits, and data paths are functional between -40 °C to 125 °C
- In-situ real-time monitoring and receive data eye voltage histogram
- Built in PRBS generators and checkers along with custom pattern generation
- ATPG Mux Scan support for digital logic
- IEEE 1149.6 JTAG boundary scan for SerDes pins
- Built-in BER monitor including a 40-bit counter to count the total number of bits received and a 30-bit counter to count the total number of errors detected by a pattern checker
- Internal serial loopback and parallel loopback support
- Interfaces available for connection to a JTAG TAP controller or through a simple parallel read/write port
- Analog and digital test bus
- PMA Hard Macro and Design Kit
- Verilog models
- LEF abstracts (.lef)
- Timing models (.lib)
- CDL netlists (.cdl)
- ATPG models
- IBIS-AMI models
- GDSII layout
- DRC & LVS reports
- Datasheet
- SoC integration guide
- Optional design integration and bring-up support services
Comprehensive chip and system design reviews
- Kickoff/program review
- Floor plan review
- Test/characterization plan review
- Package design review
- Board design review
- Final chip integration review
- Bring-up and test review
Engineering design services
- Package design
- System board layout
- Statistically-based signal and power integrity analysis
Rambus 112G XSR and LR SerDes PHYs
The virtuous cycle of increased computing power enabling new applications which demand more computing power continues unabated. Today, applications spanning AI, autonomous vehicles, video streaming, AR and VR all demand more bandwidth, lower latencies and higher speeds. In response, the SoCs powering the terabit routers and switches at the heart of the network must run even faster. The upgrade to 112G SerDes represents the latest advancement in high-speed signaling technology enabling communication within and between network devices.
Protocol Compatibility
| Protocol | Data Rate (Gbps) | Application |
|---|---|---|
| CEI112G-XSR | 72-116 | Data center and networking |
| CEI112G-VSR | 72-116 | Data center and networking |
| CEI56G-XSR-NRZ | 36-58 | Data center and networking |
| CEI56G-XSR | 36-58 | Data center and networking |
| CEI56G-VSR | 36-58 | Data center and networking |
| CEI28G-VSR | 19.6-28.1 | Data center and networking |
Inventions
Phase Interpolator-Based CDR
Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.
Resources
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