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Interface IP

112G XSR Multi-protocol SerDes PHY

A high-bandwidth, ultra-low power SerDes PHY solution for extremely short reach (XSR) 112G inter-die connections in system in package (SiP) devices serving next-generation networking and hyperscale data center applications.

How the 112G XSR PHY works

The Rambus 112G XSR Multi-Protocol SerDes (MPS) PHY is a comprehensive IP solution designed to provide best-in-class performance for the high-bandwidth connections between die or chiplets in SiP devices. The 112G MPS PHY supports PAM-4 and NRZ signaling and data rates from 25 to 112 Gbps. It is tailored for the ultra-low power and area requirements of die-to-die interfaces.

112G XSR SerDes PHY Subsystem Example
112G XSR SerDes PHY Subsystem Example

The 112G XSR MPS PHY is designed with a system-oriented approach, maximizing flexibility in today’s most challenging system environments including specifically:

  • Die-to-die (D2D) interfaces
  • Die-to-optical engine (D2OE) interfaces

Available in advanced 7nm FinFET process.

Solution Offerings

Rambus 112G XSR and LR SerDes PHYs eBook cover

Rambus 112G XSR and LR SerDes PHYs

The virtuous cycle of increased computing power enabling new applications which demand more computing power continues unabated. Today, applications spanning AI, autonomous vehicles, video streaming, AR and VR all demand more bandwidth, lower latencies and higher speeds. In response, the SoCs powering the terabit routers and switches at the heart of the network must run even faster. The upgrade to 112G SerDes represents the latest advancement in high-speed signaling technology enabling communication within and between network devices.

Protocol Compatibility

ProtocolData Rate (Gbps) Application
CEI112G-XSR72-116Data center and networking
CEI112G-VSR72-116Data center and networking
CEI56G-XSR-NRZ36-58Data center and networking
CEI56G-XSR36-58Data center and networking
CEI56G-VSR36-58Data center and networking
CEI28G-VSR19.6-28.1Data center and networking


Phase Interpolator-Based CDR

Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.