The Rambus 112G XSR Multi-Protocol SerDes (MPS) PHY is a comprehensive IP solution designed to provide best-in-class performance for the high-bandwidth connections between die or chiplets in SiP devices. The 112G MPS PHY supports PAM-4 and NRZ signaling and data rates from 25 to 112 Gbps. It is tailored for the ultra-low power and area requirements of die-to-die interfaces.
112G XSR SerDes PHY Subsystem Example
The 112G XSR MPS PHY is designed with a system-oriented approach, maximizing flexibility in today’s most challenging system environments including specifically:
Available in advanced 7nm FinFET process.
Comprehensive chip and system design reviews
Engineering design services
|Protocol||Data Rate (Gbps)||Application|
|CEI112G-XSR||72-116||Data center and networking|
|CEI112G-VSR||72-116||Data center and networking|
|CEI56G-XSR-NRZ||36-58||Data center and networking|
|CEI56G-XSR||36-58||Data center and networking|
|CEI28G-VSR||19.6-28.1||Data center and networking|
The virtuous cycle of increased computing power enabling new applications which demand more computing power continues unabated. Today, applications spanning AI, autonomous vehicles, video streaming, AR and VR all demand more bandwidth, lower latencies and higher speeds. In response, the SoCs powering the terabit routers and switches at the heart of the network must run even faster. The upgrade to 112G SerDes represents the latest advancement in high-speed signaling technology enabling communication within and between network devices.
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