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12G Multi-protocol SerDes PHY
The 12G Multi-protocol SerDes PHYs are designed to deliver high interface speed in challenging system environments. Optimized for power and area at peak bandwidth, our PHYs enable differentiation while maintaining compatibility with a broad range of industry standards.
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Product BriefHow the 12G PHY works
The Rambus 12G Multi-protocol SerDes (MPS) PHYs are a general-purpose, high-speed serial link transceiver subsystem that support data rates from 1.25 Gbps to 12 Gbps. Optimized for power and area in high-loss channels, our 12G MPS PHYs are suitable for a broad range of enterprise-class systems.
The PHYs include a PMA hard macro that supports a broad range of networking protocols as well as a PCS-BIST soft macro for PCIe that is PIPE4 compliant. They have a minimal set of broadside control and is configurable in x2, x4 and x8 lane configurations. This gives the PHYs improved flexibility and support for a wide range of applications.
The 12G SerDes PHY utilizes transmit and receive equalization, data rate negotiation, and equalization adaptation to improve system margin and performance. This ensures that data is recovered even in the presence of channel and system interference.
Available on TSMC, Global Foundry, and Samsung process nodes.
SerDes Signal Integrity Challenges at 28Gbps and Beyond
Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol. With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation.
Solution Offerings
- Duplex lane configurations of x2, x4, and x8
- Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
- Support for AC-coupled interfaces
- Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
- BER of 10-15 for CEI11-LR/SR and BER of 10-12 for SFI, XFI, PCIe and Gbe protocols
- A wide range of PLL multiplication supporting low reference clock frequencies
- Flexible ASIC clocking
- Tight skew control of 2UI between lanes of the PMA
- 3-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
- Continuous time linear equalizer (CTLe) with programmable settings providing up to 12dB gain peaking at Nyquist frequencies
- 8-tap Rx dFe (decision feedback equalizer)
- Second-order CDR meeting SSC and RX sinusoidal jitter requirements
- Expandable register interface enabling communication with multiple PMAs and PCS-bIST soft macros
- Built-in Self Test (BIST) with ATPG and AC/DC boundary scan support
- Built-in PRBS pattern generation and checking for standalone loopback testing
- In-situ real-time monitoring and receive data eye schmoo
- Operation across a wide temperature range (-40 C to +125 C)
- PMA Hard Macro
- Verilog models
- LEF abstracts (.lef)
- Timing models (.lib)
- CDL netlists (.cdl)
- ATPG models
- IBIS-AMI models
- GDSII layout
- DRC & LVS reports
- PCS-BIST Soft Macro
- RTL model
- Datasheet
- SoC Integration guide
- Optional design integration and bring-up support services
Comprehensive Chip and System Design Reviews
- Kickoff/Program Review
- Floor plan Review
- Test/Characterization Plan Review
- Package Design Review
- Board Design Review
- Final Chip Integration Review
- Bring-up and Test Review
Engineering Design Services:
- Package design
- System board layout
- Statistically-based signal and power integrity analysis
Protocol Compatibility
| Protocol | Data Rate (Gbps) | Application |
|---|---|---|
| PCIe1/2/3 | 2.5, 5, 8 | Graphics cards and high-bandwidth peripherals |
| 10GBase-KR | 10.3125 | Copper backplane networking |
| 1000Base-KX | 1.25 | Backplane and copper cable networking |
| 10GBase-KX4 | 3.125,6.25 | Copper backplane networking |
| XAUI/2xXAUI | 3.125, 6.25 | Chip-to-Chip connectivity |
| SAS 12G | 1.5, 3, 6, 12 | Server storage |
| SATA | 1.5, 3, 6 | Personal and server storage |
| CEI6 – SR/LR | 4.976 – 6.375 | Telecom and networking |
| CEI11-SR, LR | 9.95-11.2 | Telecom and networking |
| CPRI | 0.614 – 9.83 | Wireless base stations |
| JESD 204B | 3.125 – 12 | High-speed data converter connectivity |
| XFI/SFI | 9.95-11.2 | XFP and SFP+ Optical Modules |
| Interlaken 6G/10 G | 4.976-6.375, 10.3125 | Networking |
Inventions
Phase Interpolator-Based CDR
Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.
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