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28G Multi-protocol SerDes PHY
The 28G Multi-protocol SerDes (MPS) PHY is a comprehensive 100 Gigabit Ethernet (GbE) solution that is optimized for power and area in long-reach channels typical of networking and data center applications.
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Product BriefHow the 28G PHY works
The Rambus 28G MPS PHY is a comprehensive IP solutions that delivers enterprise-class performance across the challenging signaling environments typical of networking and server systems. With high performance and multi-protocol compatibility, the PHY supports data rates from 1.25 to 28.1 Gbps across copper and backplane channels with more than 30dB channel insertion loss in a wide range of industry-standard interconnect protocols. It features application-specific optimization enabled by an efficient and scalable architecture with adaptive and programmable receive equalization, and support for transmit FIR adaptation.
The 28G MPS PHY is designed with a system-oriented approach, taking the interface, interconnect and channel into account when optimizing performance and features to maximize flexibility in today’s most challenging system environments and applications. This makes the PHY ideal for many long-reach, copper and backplane system environments.
SerDes Signal Integrity Challenges at 28Gbps and Beyond
Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol. With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation.
Solution Offerings
- Supports data rates in the range of 1.25 to 28.1 Gbps
- Optimized for low-power operation and north/south die-edge placement
- AC-coupled RX front end with on-chip capacitors
- Flexible ASIC interface for sharing impedance codes among multiple PMA hard macros and reducing the number of external reference resistors for on-chip impedance calibration
- Duplex lane configurations of x4 and x1
- An LC-PLL providing a wide range of operating frequencies
- Wide range programmable multipliers for reference clock multiplication
- Differential reference clock input selectively sourced from C4 or internal ASIC interface pins
- Flexible ASIC clocking
- Programmable clock outputs from the PLL to the ASIC core
- Parallel data, transmitted to the PMA, synchronized to the transmit parallel data clock from the ASIC core
- Tight lane skew control in the PMA
- Adaptive receive equalizer with programmable settings providing up to 12dB of CTLE and 8-tap DFE support
- Support transmit FIR adaptation through back channel for Ethernet applications
- Embedded microcontroller for improved system configuration loads
- Built-in Self Test (BIST) support
- At-speed functional test capability with low-speed reference clocks
- Built-in PRBS15/31 and custom pattern generation and checking for standalone testing
- Internal serial loopback with optional phase advancing
- Parallel loopback supported within the PMA
- In-situ real-time monitoring and receive data eye schmoo through an adaptive receive sampler
- ATPG Mux Scan support for digital logic
- IEEE 1149.6 JTAG boundary scan for serial link pins
- Multiple interfaces for the access of PMA registers
- Direct register control of all PMA functionality, as well as extended features
- Interfaces available for connection to a JTAG TAP controller or through a simple parallel read/write port
- Optional MDIO interface can be provided as required for Ethernet standard PHYs
- PHY spec compliance across a wide operating junction temperature range (-20 to 125 °C). PLLs, bias circuits, and data path are functional between -40 and 125 °C
- PMA hard macro
- Verilog models
- LEF abstracts (.lef)
- Timing models (.lib)
- CDL netlists (.cdl)
- ATPG models
- IBIS-AMI models
- GDSII layout
- DRC & LVS reports
- Datasheet
- SoC integration guide
Comprehensive chip and system design reviews
- Kickoff/program review
- Floor plan review
- Test/characterization plan review
- Package design review
- Board design review
- Final chip integration review
- Bring-up and test review
Engineering design services:
- Package design
- System board layout
- Statistically-based signal and power integrity analysis
Protocol Compatibility
| Protocol | Data Rate (Gbps) | Application |
|---|---|---|
| 100GBASE-KR4 | 25.78125 | Copper backplane networking |
| 10GBase-KR | 10.3125 | Copper backplane networking |
| CEI-28G-VSR | 19.6-28.1 | Telecom and networking |
| CEI-28G-SR | 19.9-28.05 | Telecom and networking |
| CEI-28G-MR | 19.9-28.1 | Telecom and networking |
| CEI-25G-LR | 19.9-25.8 | Telecom and networking |
| CEI6-SR | 4.976-6.375 | Telecom and networking |
| CEI11-SR, LR | 9.95-11.2 | Telecom and networking |
| XAUI/2xXAUI | 3.125, 6.25 | Chip-to-Chip connectivity |
| Interlaken 6 G | 4.976-6.375 | Networking |
| JESD 204B/C | 3.125 – 25 | High-speed data converters connectivity |
| CAUI (10x) XLAUI (4x) | 10.3125 | Chip-to-Chip connectivity |
| CAUI-4 | 28.1 | Chip-to-Chip connectivity |
| SFI / XFI | 10.3125 | XFP and SFP+ optical modules |
| CPRI | 1.22 – 24.33 | Wireless base stations |
| Infiniband EDR | 25.78125 | High-performance server connectivity |
| Infiniband FDR | 14.0625 | High-performance server connectivity |
Inventions
Phase Interpolator-Based CDR
Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.
Resources
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