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Interface IP

32G Multi-protocol SerDes PHY

The 32G Multi-protocol SerDes (MPS) PHY is designed to meet the power efficiency and performance requirements of next-generation, high-speed wireline and wireless 5G infrastructure applications.

How 32G works

The Rambus 32G MPS PHY is a comprehensive IP solution that is optimized for power and area in long-reach channels typical of communications, networking and data center applications. With high performance and multi-protocol compatibility, the PHY supports data rates from 2.5 to 32 Gbps in a wide range of industry-standard interconnect protocols including PCIe 4.0, JESD204B/C, CPRI and Ethernet. It features application-specific optimization enabled by an efficient and scalable architecture with adaptive and programmable receive equalization, and support for transmit FIR adaptation.

32G SerDes PHY Subsystem diagram

32G MPS PHY Subsystem Example

The 32G MPS PHY is designed with a system-oriented approach, taking the interface, interconnect and channel into account when optimizing performance and features that maximize flexibility in today’s most challenging system environments. This makes the PHY ideal for high-performance wireline and 5G wireless infrastructure applications.

Solution Offerings

  • Supports data rates of 2.5 to 32 Gbps
  • Available in GLOBALFOUNDRIES 22FDX® process node
  • Optimized for low-power operation and north/south die-edge placement
  • AC-coupled RX front end with on-chip capacitors
  • Flexible ASIC interface for sharing impedance codes among multiple PMA hard macros and reducing the number of external reference resistors for impedance calibration
  • Duplex lane configurations of x4 and x1
  • LC-PLLs provide a wide range of operating frequencies
  • Wide range programmable multipliers for reference clock multiplication
  • Differential reference clock inputs are selectively sourced from C4 or internal ASIC interface pins
  • Flexible ASIC clocking
  • Programmable clock outputs from the PLL to the ASIC core
  • Parallel data, transmitted to the PMA, synchronized to the transmit parallel data clock from the ASIC core
  • Tight lane skew control in the PMA
  • Adaptive receive equalizer with programmable CTLE and DFE support
  • Support transmit FIR adaptation through back channel for Ethernet applications
  • Built-in Self Test (BIST) support
  • At-speed functional test capability with low-speed reference clocks
  • Built-in PRBS15/31 and custom pattern generation and checking for standalone testing
  • Internal serial loopback with optional phase advancing
  • Parallel loopback supported within the PMA
  • In-situ real-time monitoring and receive data eye schmoo through an adaptive receive sampler
  • ATPG Mux Scan support for digital logic
  • IEEE 1149.6 JTAG boundary scan for serial link pins
  • Multiple interfaces for the access of PMA registers
  • Provides direct register control of all PMA functionality, as well as extended features
  • Interfaces available for connection to a JTAG TAP controller or through a simple parallel read/write port
  • Optional MDIO interface can be provided as required for Ethernet standard PHYs
  • PMA hard macro and design kit
    • Verilog models
    • LEF abstracts (.lef)
    • Timing models (.lib)
    • CDL netlists (.cdl)
    • ATPG scan and IEEE 1149.6 AC boundary scan
    • IBIS-AMI models
    • GDSII layout
    • DRC and LVS reports
  • Datasheet
  • SoC integration guide
  • Optional design integration and bring-up support services

Comprehensive chip and system design reviews

  • Kickoff/program review
  • Floor plan review
  • Test/characterization plan review
  • Package design review
  • Board design review
  • Final chip integration review
  • Bring-up and test review
 

 Engineering design services

  • Package design
  • System board layout
  • Statistically-based signal and power integrity analysis

Protocol Compatibility

ProtocolData Rate (Gbps) Application
PCIe 4.016Hyperscale data center and big data applications
100GBASE-KR425.78125Copper backplane networking
40GBase-KR410.3125Copper backplane networking
10GBase-KR10.3125Copper backplane networking
CEI-28G-VSR19.6-28.1Telecom and networking
CEI-28G-SR19.9-28.05Telecom and networking
CEI-28G-MR19.9-28.1Telecom and networking
CEI-25G-LR19.9-25.8Telecom and networking
CEI11-SR, LR9.95-11.2Telecom and networking
JESD 204B/C3.125 – 32High-speed data converters connectivity
CPRI1.22 – 24.33Wireless base stations
SerDes Signal Integrity Challenges at 28Gbps and Beyond

SerDes Signal Integrity Challenges at 28Gbps and Beyond

Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol. With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation. For PAM4 signals, the baud rate equals one-half the bit rate and the Nyquist frequency equals one-fourth the bit rate. Compared to PAM2/NRZ, PAM4 cuts the bandwidth for a given data rate in half by transmitting two bits in each symbol. This allows engineers to double the bit rate in the channel without doubling the required bandwidth.
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Inventions

Phase Interpolator-Based CDR

Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.

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