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Interface IP

32G Multi-protocol SerDes PHY

The 32G Multi-protocol SerDes (MPS) PHY is designed to meet the power efficiency and performance requirements of next-generation, high-speed wireline and wireless 5G infrastructure applications.

How the 32G PHY works

The Rambus 32G MPS PHY is a comprehensive IP solution that is optimized for power and area in long-reach channels typical of communications, networking and data center applications. With high performance and multi-protocol compatibility, the PHY supports data rates from 2.5 to 32 Gbps in a wide range of industry-standard interconnect protocols including PCIe 4.0, JESD204B/C, CPRI and Ethernet. It features application-specific optimization enabled by an efficient and scalable architecture with adaptive and programmable receive equalization, and support for transmit FIR adaptation.

32G SerDes PHY Subsystem diagram
32G MPS PHY Subsystem Example

The 32G MPS PHY is designed with a system-oriented approach, taking the interface, interconnect and channel into account when optimizing performance and features that maximize flexibility in today’s most challenging system environments. This makes the PHY ideal for high-performance wireline and 5G wireless infrastructure applications.

Solution Offerings

SerDes Signal Integrity Challenges at 28Gbps and Beyond

SerDes Signal Integrity Challenges at 28Gbps and Beyond

Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol. With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation. 

Protocol Compatibility

ProtocolData Rate (Gbps) Application
PCIe 4.016Hyperscale data center and big data applications
100GBASE-KR425.78125Copper backplane networking
40GBase-KR410.3125Copper backplane networking
10GBase-KR10.3125Copper backplane networking
CEI-28G-VSR19.6-28.1Telecom and networking
CEI-28G-SR19.9-28.05Telecom and networking
CEI-28G-MR19.9-28.1Telecom and networking
CEI-25G-LR19.9-25.8Telecom and networking
CEI11-SR, LR9.95-11.2Telecom and networking
JESD 204B/C3.125 – 32High-speed data converters connectivity
CPRI1.22 – 24.33Wireless base stations

Inventions

Phase Interpolator-Based CDR

Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.