At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
32G Multi-protocol SerDes PHY
The 32G Multi-protocol SerDes (MPS) PHY is designed to meet the power efficiency and performance requirements of next-generation, high-speed data center, networking and 5G infrastructure applications.
Contact
32G MPS PHYHow the 32G PHY works
The Rambus 32G MPS PHY is a comprehensive IP solution that is optimized for power and area in long-reach 30dB channels typical of communications, networking and data center applications. With high performance and multi-protocol compatibility, the PHY supports data rates from 2.5 to 32 Gbps in a wide range of industry-standard interconnect protocols including PCIe 4.0, JESD204B/C, CPRI and Ethernet. It features application-specific optimization enabled by an efficient and scalable architecture with adaptive and programmable receive equalization, and support for transmit FIR adaptation.
The 32G MPS PHY is designed with a system-oriented approach, taking the interface, interconnect and channel into account when optimizing performance and features that maximize flexibility in today’s most challenging system environments. This makes the PHY ideal for high-performance wireline and 5G wireless infrastructure applications.
For Ultra-Low Power 32G Designs
Rambus also offers an ultra-low power 32G MR MPS PHY (formerly AnalogX AXLinkIO MP) for medium-reach channels up to 20dB insertion loss. This PHY solution supports PCIe 5.0 and earlier generations, Ethernet to 25.78125 Gbps, Interlaken, JESD 204B/C, CPRI and more. It offers the industry’s best power, area and latency in its class for next-generation applications with the most demanding PPA requirements. It is available on advanced FinFET process nodes.
Solution Offerings
- Supports data rates of 2.5 to 32 Gbps
- Available in GLOBALFOUNDRIES 22FDX® process node
- Optimized for low-power operation and north/south die-edge placement
- AC-coupled RX front end with on-chip capacitors
- Flexible ASIC interface for sharing impedance codes among multiple PMA hard macros and reducing the number of external reference resistors for impedance calibration
- Duplex lane configurations of x4 and x1
- LC-PLLs provide a wide range of operating frequencies
- Wide range programmable multipliers for reference clock multiplication
- Differential reference clock inputs are selectively sourced from C4 or internal ASIC interface pins
- Flexible ASIC clocking
- Programmable clock outputs from the PLL to the ASIC core
- Parallel data, transmitted to the PMA, synchronized to the transmit parallel data clock from the ASIC core
- Tight lane skew control in the PMA
- Adaptive receive equalizer with programmable CTLE and DFE support
- Support transmit FIR adaptation through back channel for Ethernet applications
- Built-in Self Test (BIST) support
- At-speed functional test capability with low-speed reference clocks
- Built-in PRBS15/31 and custom pattern generation and checking for standalone testing
- Internal serial loopback with optional phase advancing
- Parallel loopback supported within the PMA
- In-situ real-time monitoring and receive data eye schmoo through an adaptive receive sampler
- ATPG Mux Scan support for digital logic
- IEEE 1149.6 JTAG boundary scan for serial link pins
- Multiple interfaces for the access of PMA registers
- Provides direct register control of all PMA functionality, as well as extended features
- Interfaces available for connection to a JTAG TAP controller or through a simple parallel read/write port
- Optional MDIO interface can be provided as required for Ethernet standard PHYs
- PMA hard macro and design kit
- Verilog models
- LEF abstracts (.lef)
- Timing models (.lib)
- CDL netlists (.cdl)
- ATPG scan and IEEE 1149.6 AC boundary scan
- IBIS-AMI models
- GDSII layout
- DRC and LVS reports
- Datasheet
- SoC integration guide
- Optional design integration and bring-up support services
Comprehensive chip and system design reviews
- Kickoff/program review
- Floor plan review
- Test/characterization plan review
- Package design review
- Board design review
- Final chip integration review
- Bring-up and test review
Engineering design services
- Package design
- System board layout
- Statistically-based signal and power integrity analysis
Protocol Compatibility
| Protocol | Data Rate (Gbps) | Application |
|---|---|---|
| PCIe 4.0 | 16 | Hyperscale data center and big data applications |
| 100GBASE-KR4 | 25.78125 | Copper backplane networking |
| 40GBase-KR4 | 10.3125 | Copper backplane networking |
| 10GBase-KR | 10.3125 | Copper backplane networking |
| CEI-28G-VSR | 19.6-28.1 | Telecom and networking |
| CEI-28G-SR | 19.9-28.05 | Telecom and networking |
| CEI-28G-MR | 19.9-28.1 | Telecom and networking |
| CEI-25G-LR | 19.9-25.8 | Telecom and networking |
| CEI11-SR, LR | 9.95-11.2 | Telecom and networking |
| JESD 204B/C | 3.125 – 32 | High-speed data converters connectivity |
| CPRI | 1.22 – 24.33 | Wireless base stations |
Resources
Videos
