Memory Interfaces Icon

Interface IP

40G USR and C2C SerDes PHYs

High-bandwidth, extremely low power SerDes PHY solutions for ultra-short reach (USR) and Chip-to-Chip (C2C) 40G interconnects serving next-generation networking and data center applications.

How the 40G PHYs work

The Rambus 40G USR and C2C SerDes PHYs (formerly AnalogX AXDieIO and AXLinkIO) offer the industry’s lowest power, area and latency for operation from 1 to 40 Gbps. The 40G USR PHY offers a breakthrough power efficiency of < 1 mW/Gbps for channels up to 8dB in die-to-die (D2D) and ultra-short reach implementations. The 40G C2C PHY supports channel loss of up to 16dB with an efficiency of 1.5 mW/Gbps. These power and area optimized IP solutions help designers meet aggressive PPA budgets for next-generation applications.

40G SerDes PHY Subsystem Example
40G SerDes PHY Subsystem Example

Both PHYs support lane configurations of up to x20 per macro and require no external components nor special packaging. 

These silicon-proven solutions are available in advanced FinFET process nodes.

CXL Memory Interconnect Initiative: Enabling a New Era of Data Center Architecture

CXL Memory Interconnect Initiative: Enabling a New Era of Data Center Architecture

In response to an exponential growth in data, the industry is on the threshold of a groundbreaking architectural shift that will fundamentally change the performance, efficiency and cost of data centers around the globe. Server architecture, which has remained largely unchanged for decades, is taking a revolutionary step forward to address the growing demand for data and the voracious performance requirements of advanced workloads. 

Solution Offerings

Related Markets & Applications