Memory Interfaces Icon

Interface IP

32G C2C SerDes PHY

High-bandwidth, extremely low power SerDes PHY solution for ultra-short reach (USR) and Chip-to-Chip (C2C) 32G interconnects serving next-generation networking and data center applications.

How the 32G C2C PHY works

The Rambus 32G C2C SerDes PHY (formerly AnalogX AXDieIO) offer the industry’s lowest power, area and latency for operation from 1 to 32 Gbps. The 32G C2C PHY offers a breakthrough power efficiency for channels up to 8dB in die-to-die (D2D) and ultra-short reach implementations. It supports channel loss of up to 16dB with an excellent power efficiency. This power and area optimized IP solution helps designers meet aggressive PPA budgets for next-generation applications.

32G SerDes PHY Subsystem Example
32G SerDes PHY Subsystem Example

The PHY supports lane configurations of up to x20 per macro and requires no external components nor special packaging. 

This silicon-proven solution is available in advanced FinFET process nodes.

CXL Memory Interconnect Initiative: Enabling a New Era of Data Center Architecture

CXL Memory Interconnect Initiative: Enabling a New Era of Data Center Architecture

In response to an exponential growth in data, the industry is on the threshold of a groundbreaking architectural shift that will fundamentally change the performance, efficiency and cost of data centers around the globe. Server architecture, which has remained largely unchanged for decades, is taking a revolutionary step forward to address the growing demand for data and the voracious performance requirements of advanced workloads. 

Solution Offerings

Related Markets & Applications