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Interface IP

56G LR Multi-protocol SerDes PHY

The 56G Multi-protocol SerDes (MPS) PHY is a comprehensive PAM-4 solution with available adjustable power through an integrated ADC that provides for future scalability in long-reach data center applications.

How the 56G PHY works

The Rambus 56G MPS PHY is a PAM-4 and NRZ compliant IP solution that provides reliable performance across challenging long-reach data center environments. A 28 GS/s ADC integrated directly into the architecture enables future scalability and extended reach. With high performance and multi-protocol compatibility, the PHY supports data rates from 9.95 to 58 Gbps across copper and backplane channels with more than 35dB channel insertion loss. Flexible system design is enabled through the ability to control the power consumption of the PHY.

56G MPS PHY Subsystem Example

56G MPS PHY Subsystem Example

The 56G MPS PHY is designed with a system-oriented approach, taking the interface, interconnect and channel into account when optimizing performance and features to maximize flexibility in today’s most challenging system environments and applications. This makes the PHY ideal for many long-reach, copper and backplane system environments.

Available in advanced FINFET process.

Rambus 112G XSR and LR SerDes PHYs eBook cover

Rambus 112G XSR and LR SerDes PHYs

The virtuous cycle of increased computing power enabling new applications which demand more computing power continues unabated. Today, applications spanning AI, autonomous vehicles, video streaming, AR and VR all demand more bandwidth, lower latencies and higher speeds. In response, the SoCs powering the terabit routers and switches at the heart of the network must run even faster. The upgrade to 112G SerDes represents the latest advancement in high-speed signaling technology enabling communication within and between network devices.

Solution Offerings

  • Supports up to 8 duplex lanes and data rates from 9.95 to 56 Gbps
  • Embedded micro-processor enables firmware-controlled PMA configuration, initialization and adaptation for maximum flexibility and minimum ASIC integration effort
  • RX front end with on-chip capacitors supports both AC-coupled and DC-coupled channels
  • Configurable architecture enables maximum power saving for low and medium loss channels
  • Flexible ASIC interface for sharing impedance codes among multiple PMAs and reducing the number of external reference resistors for on-chip impedance calibration
  • Programmable TX/RX equalizers including:
    • 4-tap transmit FFE (2-tap pre-cursor taps, main tap and 1 post-cursor tap) for extended channel reach
    • Combined 12dB peaking gain of analog front end with CTLE
    • Multi-tap digital FFE and DFE
  • A centralized LC-PLL supports a wide range of reference clock frequencies and lane operating frequencies
  • Differential reference clock inputs are selectively sourced from dedicated pins or internal ASIC interface pins
  • Direct register control is available for all PMA functions
  • Vertical poly direction supports placement along all edges in an ASIC
  • PMA is spec compliant across a wide operating junction temperature range (-20 to 105 °C). PLLs, bias circuits, and data paths are functional between -40 to 125 °C
  • In-situ real-time monitoring and receive data eye voltage histogram
  • Built in PRBS generators and checkers along with custom pattern generation
  • ATPG Mux Scan support for digital logic
  • IEEE 1149.6 JTAG boundary scan for serial link pins
  • Built-in BER monitor including a 40-bit counter to count the total number of bits received and a 30-bit counter to count the total number of errors detected by a pattern checker
  • Internal serial loopback and parallel loopback support
  • Interfaces available for connection to a JTAG TAP controller or through a simple parallel read/write port
  • Analog and digital test bus
  • PMA hard macro
    • Verilog models
    • LEF abstracts (.lef)
    • Timing models (.lib)
    • CDL netlists (.cdl)
    • ATPG models
    • IBIS-AMI models
    • GDSII layout
    • DRC and LVS reports
  • Datasheet
  • SoC integration guide
  • Optional design integration and bring-up support services

Protocol Compatibility

ProtocolData Rate (Gbps) Application
400GAUI-8 LR53.125Telecom and networking
400GAUI-8 MR53.125Telecom and networking
100G-KR4 LR25.78125Telecom and networking
10G-KR10.3125Telecom and networking
CEI56G-LR36 – 58Copper backplane networking
CEI56G-MR36 – 58Chip-to-Chip connectivity
CEI28G-MR19.9 – 28.1Copper backplane networking
CEI25G-LR19.9 – 25.8Copper backplane networking
CEI11G-LR9.95 – 11.2Copper backplane networking


Phase Interpolator-Based CDR

Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.

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