Effectively expands main memory for high-capacity workloads
Through the CXL Memory Interconnect Initiative, Rambus is researching and developing solutions to enable a new era of data center performance and efficiency. Announced on June 16, 2021, this initiative is the latest chapter in the 30-year history of Rambus leadership in the development of breakthrough memory and chip-to-chip interconnect technology and products.
Realization of the chip solutions needed for the memory expansion and pooling use cases, and further those needed for server disaggregation and composability, will require the synthesis of a number of critical technologies. Rambus has been researching memory solutions for disaggregated architectures for close to a decade and leverages a system-aware design approach to solve these next-generation challenges. This initiative brings together our expertise in memory and SerDes subsystems, semiconductor and network security, high-volume memory interface chips and compute system architectures to develop breakthrough interconnect solutions for the future data center.
In response to an exponential growth in data, the industry is on the threshold of a groundbreaking architectural shift that will fundamentally change the performance, efficiency and cost of data centers around the globe. Server architecture, which has remained largely unchanged for decades, is taking a revolutionary step forward to address the growing demand for data and the voracious performance requirements of advanced workloads.
Driven by a confluence of megatrends, global data traffic is increasing at an exponential rate. For example, 5G networks are enabling billions of AI-powered IoT devices untethered from wired networks. Nowhere is the impact of all this growth being felt more intensely than in data centers. Indeed, hyperscale data centers have become the critical hubs of the global data network. DDR5 DRAM will enable the next generation of server systems providing the massive computing power of hyperscale and enterprise data centers. Learn about the benefits of DDR5 memory and the design considerations for implementing DDR5 DIMMs.