Memory IP Solutions
Our family of memory PHYs offers a number of compelling benefits to chip and system designers alike, including reduced power consumption, increased data rates and improved cost-effectiveness – giving designers the advantage of increased margin and flexibility. These solutions are applicable to a broad range of applications spanning from mobile, to consumer to enterprise.
Rambus PHYs incorporate innovations such as FlexPhase™ timing adjustment circuits, output driver and On Die Termination (ODT) calibration that allow system designers to optimize for their unique requirements.
As part of a complete solution, our PHYs contain all of the necessary components for robust operation and ease of integration. They consist of hard macros of the command/address (C/A) and 8-bit data cells, and include IO pads, phase lock loops (PLL), power mode management (PMM), transmit and receive paths, clock distribution, control logic, power distribution and electrostatic discharge (ESD) protection circuitry. Outside of the PHY itself, our solutions also include complete documentation and access to our in-house experts for optional design integration and bring-up support services to make integration as straightforward as possible.