Memory + Interfaces

12 Gbps Multi-protocol SerDes PHY

The 12 Gbps Multi-protocol SerDes PHYs, including recently acquired Snowbush IP, are designed to deliver high interface speed in challenging system environments. Optimized for power and area at peak bandwidth, our PHYs enable differentiation while maintaining compatibility with a broad range of industry standards.

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Product Brief

R+ 1.25 – 11.2 Gbps Multi-protocol Serial Link PHY block diagram

12G PHY Subsystem Example

How it works

The Rambus 12 Gbps Multi-Protocol SerDes (MPS) PHYs are a general-purpose, high-speed serial link transceiver subsystem that support data rates from 1.25 Gbps to 12 Gbps. Optimized for power and area in high-loss channels, our 12G MPS PHYs are suitable for a broad range of enterprise-class systems.

The PHYs include a PMA hard macro that supports a broad range of networking protocols as well as a PCS-BIST soft macro for PCIe that is PIPE4 compliant. They have a minimal set of broadside control and is configurable in x2, x4 and x8 lane configurations. This gives the PHYs improved flexibility and support for a wide range of applications.

The 12G SerDes PHY utilizes transmit and receive equalization, data rate negotiation, and equalization adaptation to improve system margin and performance. This ensures that data is recovered even in the presence of channel and system interference.

Available on TSMC, Global Foundry, and Samsung process nodes.

Solution Offerings

Protocol Compatibility 

Protocol Data Rate (Gbps) Application
PCIe1/2/3 2.5, 5, 8 Graphics cards and high-bandwidth peripherals
10GBase-KR 10.3125 Copper backplane networking
1000Base-KX 1.25 Backplane and copper cable networking
10GBase-KX4 3.125,6.25 Copper backplane networking
XAUI/2xXAUI 3.125, 6.25 Chip-to-Chip connectivity
SAS 12G 1.5, 3, 6, 12 Server storage
SATA 1.5, 3, 6 Personal and server storage
CEI6 – SR/LR 4.976 – 6.375 Telecom and networking
CEI11-SR, LR 9.95-11.2 Telecom and networking
CPRI 0.614 – 9.83 Wireless base stations
JESD 204B 3.125 – 12 High-speed data converter connectivity
XFI/SFI 9.95-11.2 XFP and SFP+ Optical Modules
Interlaken 6G/10 G 4.976-6.375, 10.3125 Networking

Inventions

Phase Interpolator-based CDR

Phase-Interpolator-based-Clock-and-Data-Recovery-CDR-thumbnail
Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.

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