Memory + Interfaces

28 Gbps Multi-protocol SerDes PHY

The 28 Gbps Multi-protocol SerDes PHYs, including recently acquired Snowbush IP, is a comprehensive 100 Gigabit Ethernet solution that is optimized for power and area in long-reach channels typical of networking and data center applications.

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Product Brief

R+ 1.25-16 Gbps Multi-protocol Serial Link PHY block diagram

28G PHY Subsystem Example

How it works

The Rambus 28 Gbps Multi-Protocol SerDes (MPS) PHYs are comprehensive IP solutions that deliver enterprise-class performance across the challenging signaling environments typical of networking and server systems. With high performance and multi-protocol compatibility, the PHYs support data rates from 1.25Gbps to 28.1Gbps across copper and backplane channels with more than 30dB channel insertion loss in a wide range of industry-standard interconnect protocols. They feature application-specific optimization enabled by an efficient and scalable architecture with adaptive and programmable receive equalization, and support for transmit FIR adaptation.

The 28G MPS are designed with a system-oriented approach, taking the interface, interconnect and channel into account when optimizing performance and features to maximize flexibility in today’s most challenging system environments and applications. This makes the PHYs ideal for many long-reach, copper and backplane enterprise environments.

Solution Offerings

Protocol Compatibility

Protocol Data Rate (Gbps) Application
100GBASE-KR4 25.78125 Copper backplane networking
10GBase-KR 10.3125 Copper backplane networking
CEI-28G-VSR 19.6-28.1 Telecom and networking
CEI-28G-SR 19.9-28.05 Telecom and networking
CEI-28G-MR 19.9-28.1 Telecom and networking
CEI-25G-LR 19.9-25.8 Telecom and networking
CEI6-SR 4.976-6.375 Telecom and networking
CEI11-SR, LR 9.95-11.2 Telecom and networking
XAUI/2xXAUI 3.125, 6.25 Chip-to-Chip connectivity
Interlaken 6 G 4.976-6.375 Networking
JESD 204B/C 3.125 – 25 High-speed data converters connectivity
CAUI (10x)
XLAUI (4x)
10.3125 Chip-to-Chip connectivity
CAUI-4 28.1 Chip-to-Chip connectivity
SFI / XFI 10.3125 XFP and SFP+ Optical Modules
CPRI 1.22 – 24.33 Wireless Base Stations
Infiniband EDR 25.78125 High-performance server connectivity
Infiniband FDR 14.0625 High-performance server connectivity
SerDes Signal Integrity Challenges at 28Gbps and Beyond

SerDes Signal Integrity Challenges at 28Gbps and Beyond

Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol. With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation. For PAM4 signals, the baud rate equals one-half the bit rate and the Nyquist frequency equals one-fourth the bit rate. Compared to PAM2/NRZ, PAM4 cuts the bandwidth for a given data rate in half by transmitting two bits in each symbol. This allows engineers to double the bit rate in the channel without doubling the required bandwidth.

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Inventions

Phase Interpolator-based CDR

Phase-Interpolator-based-Clock-and-Data-Recovery-CDR-thumbnail

Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.

Related Markets & Applications

Data Center