Memory + Interfaces

6 Gbps Multi-Protocol SerDes PHY

Competitive with even single protocol solutions, our 6 Gbps Multi-Protocol SerDes (MPS) PHYs, including recently acquired Snowbush IP, are a general-purpose, high-speed serial link subsystem that supports a broad range if standards with an optimized area footprint and power envelope.


Product Brief

R+ 1-6G Serial Link PHY block diagram

6G PHY Subsystem Example

How it works

The Rambus 6 Gbps Multi-Protocol SerDes (MPS) PHYs are a general-purpose, high-speed serial link subsystem that support data rates from 1.25 Gbps to 6.375 Gbps. Optimized for power and area, they can compete even with single-protocol solutions.

The PHYs include a PMA hard macro that supports a broad range of networking protocols and a PCS-BIST soft macro for PCIe that is PIPE4 compliant. They have a minimal set of broadside control and is configurable in x2, x4 and x8 lane configurations. This gives the PHYs improved flexibility and support for a wide range of applications.

The 6G PHYs feature Built-in-self-test (BIST) with PRBS checker functionality, transmit and receive equalization, and supports a wide range of reference clock multipliers to improve system margin and performance. This ensures the best signal quality and enables greater design flexibility.

Available on TSMC and Global Foundry process nodes.

Solution Offering

Protocol Compatibility

Protocol Data Rate (Gbps) Application
PCIe1/2/ 2.5, 5 Graphics cards and high-bandwidth peripherals
SATA 1/2/3 1.5, 3, 6 Personal computing and server storage
GbE 1.25 Backplane and copper cable networking
XAUI/2xXAUI 3.125, 6.25 Networking
CEI6-SR 4.976-6.375 Telecom and networking
USB 2/3 0.4, 5 Computing and peripheral connectivity
Interlaken 4.976-6.375 Networking


Phase Interpolator-based CDR


Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.

From the blog

Related Markets & Applications

Data Center