Memory + Interfaces

6 Gbps Multi-Protocol SerDes PHY

Competitive with even single protocol solutions, our 6 Gbps Multi-Protocol SerDes (MPS) PHYs, including recently acquired Snowbush IP, are a general-purpose, high-speed serial link subsystem that supports a broad range if standards with an optimized area footprint and power envelope.

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Product Brief

R+ 1-6G Serial Link PHY block diagram

6G PHY Subsystem Example

How 6G works

The Rambus 6 Gbps Multi-Protocol SerDes (MPS) PHYs are a general-purpose, high-speed serial link subsystem that support data rates from 1.25 Gbps to 6.375 Gbps. Optimized for power and area, they can compete even with single-protocol solutions.

The PHYs include a PMA hard macro that supports a broad range of networking protocols and a PCS-BIST soft macro for PCIe that is PIPE4 compliant. They have a minimal set of broadside control and is configurable in x2, x4 and x8 lane configurations. This gives the PHYs improved flexibility and support for a wide range of applications.

The 6G PHYs feature Built-in-self-test (BIST) with PRBS checker functionality, transmit and receive equalization, and supports a wide range of reference clock multipliers to improve system margin and performance. This ensures the best signal quality and enables greater design flexibility.

Available on TSMC and Global Foundry process nodes.

Solution Offering

Protocol Compatibility

ProtocolData Rate (Gbps)Application
PCIe1/2/2.5, 5Graphics cards and high-bandwidth peripherals
SATA 1/2/31.5, 3, 6Personal computing and server storage
GbE1.25Backplane and copper cable networking
XAUI/2xXAUI3.125, 6.25Networking
CEI6-SR4.976-6.375Telecom and networking
USB 2/30.4, 5Computing and peripheral connectivity
Interlaken4.976-6.375Networking

Inventions

Phase Interpolator-based CDR

Phase-Interpolator-based-Clock-and-Data-Recovery-CDR-thumbnail

Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.

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