The latest generation of the PCI Express, PCIe™ 6.0, advances performance to 64 GT/s in support of advanced workloads and networking. In this presentation, interface technology expert, Arjun Bangre will discuss the changes implemented in PCI Express 6.0, such as PAM4 signaling and low-latency forward error correction (FEC). In addition, Arjun Bangre will contrast PCIe 6.0 and 5.0 and explain how Rambus can support the PCIe interface your next design requires.
Accelerating Data Interconnects with PCI Express™ 6.0 & 5.0 Interface IP
GDDR6 Memory Enables High-Performance Inferencing
A rapid rise in the size and sophistication of inferencing models has necessitated increasingly powerful hardware deployed at the network edge and in the endpoint devices. To keep these inferencing processors and accelerators fed with data requires a state-of-the-art memory solution that delivers extremely high bandwidth. Frank Ferro will discuss the design and implementation considerations of GDDR6 memory subsystems to address the bandwidth needs of these next-generation inferencing engines.
Implementing CXL™ 2.0 Interconnect Solutions
Compute Express Link™ (CXL) has evolved rapidly since its launch in 2019 and is slated for debut in the next generation of server platforms coming later this year. While it builds on the same physical layer as PCI Express, CXL implements unique features at the controller level to enable memory cache coherency between a host and multiple types of connected devices including smart NICs, accelerators and memory expansion devices.
Memory Bandwidth for AI/ML Races Higher with HBM3
With the insatiable need for higher bandwidth in state-of-the-art AI/ML training and HPC, the HBM standard has been on a rapid pace of improvement. The newly standardized HBM3 generation doubles the data rate to 6.4 Gb/s that offers up to 819 GB/s of memory bandwidth between an accelerator and a single HBM3 DRAM device. Memory interface technology expert, Frank Ferro will discuss how the Rambus 8.4 Gb/s HBM3 Memory Subsystem can provide the headroom and scalability needed for implementing state-of-the-art HBM designs.
Advancing Computing in the Accelerator Age
Moore’s Law has been the force that has shaped the modern world enabling chips with billions of transistors. Yet today, when we need Moore’s Law more than ever, the rate of semiconductor scaling is slowing, requiring system architects to take a new approach to continue the pace of performance gains in computing. Heterogenous compute architectures with purpose-built silicon hold the key to the next great chapter of semiconductor industry as we enter the accelerator era.
Rambus RT-640 Road to ISO26262 Certification
Modern vehicles incorporate an increasing number of complex integrated circuits. Failures in automotive systems can lead to damage to property, injury or loss of life. Ensuring the reliability of electronic systems is crucial, and the ISO26262 standard documents the requirements for determining automotive functional safety. This whitepaper details the process for how Rambus achieved the ISO26262 ASIL-B certification of the RT-640 hardware security module.
