Loren Shalinsky, a Strategic Development Director at Rambus, recently penned a detailed article for Semiconductor Engineering that explores the memory-storage hierarchy. As he puts it, the hierarchy, or pyramid, is a particularly succinct method of understanding computer systems and the dizzying array of memory options available to the system designer.
Memory + Interfaces
Navigating the DDR4 adoption road map
The projected adoption rate of DDR4 as the dominant industry memory standard was a major topic of discussion at Intel’s Developer Forum earlier this month,
Future challenges for DDR4 and beyond
Ely Tsern, VP and chief technologist for the Rambus Memory and Interfaces division, has identified five key trends driving future server memory. These include Big
TECHnalysis Research talks Rambus server memory chipsets
Bob O’Donnel of TECHnalysis Research recently published a white paper describing the critical role memory server chipsets play in facilitating high-speed DDR4 designs. “With the introduction
Ely Tsern talks memory interface chipsets with The Platform
Ely Tsern, VP and chief technologist for the Rambus Memory and Interfaces division, recently sat down with Nicole Hemsoth of The Platform to discuss the
Riding Big Data waves with the R+ DDR4 Server DIMM chipset
Semiconductor Engineering editor in chief Ed Sperling has confirmed that evolving business models, acquisitions, minority investments and increasing uncertainty are creating fundamental industry shifts. “The announcement that
