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Rambus develops 56G SerDes PHY on Samsung’s 10nm LPP process

https://www.rambus.com/blogs/rambus-develops-56g-serdes-phy-on-samsungs-10nm-lpp-process/

Rambus has confirmed that its recently launched 56G SerDes PHY will be developed on Samsung’s 10nm LPP (Low-Power Plus) process technology. According to Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces Division, the 56G SerDes PHY delivers enterprise-class performance across the challenging signaling environments typical of high-speed communication systems […]

The Rambus 56 Gbps multi-protocol SerDes PHY: A closer look

https://www.rambus.com/blogs/the-rambus-56-gbps-multi-protocol-serdes-phy-a-closer-look/

Last week, we announced the launch of our 56G Multi-protocol SerDes (MPS) PHY developed on second-gen FinFET (Fin Field Effect Transistor) process technology. With a scalable ADC-based (analog-to-digital converter) architecture, the 56G SerDes FinFET PHY provides both PAM-4 and NRZ signaling, offering a flexible solution that addresses the needs of long-reach backplane requirements as the […]

Intel says DDR4 is ramping quickly

http://www.rambusblog.com/2016/08/24/intel-says-ddr4-is-ramping-quickly/#new_tab

Last week at IDF 2016, Intel executive Geof Findley presented a comprehensive overview of the memory industry ecosystem. According to Findley, DDR4 is ramping quickly and should hit 31% of shipments during the second quarter of 2016. With volume shipments kicking off in 2014, almost all servers are now shipping with DDR4, while most PCs […]

Intel says DDR4 is ramping quickly

https://www.rambus.com/blogs/intel-says-ddr4-is-ramping-quickly-2/

Last week at IDF 2016, Intel executive Geof Findley presented a comprehensive overview of the memory industry ecosystem. According to Findley, DDR4 is ramping quickly and should hit 31% of shipments during the second quarter of 2016. With volume shipments kicking off in 2014, almost all servers are now shipping with DDR4, while most PCs […]

Rambus launches R+ 28G Serial Link PHY on Samsung’s 14nm LPP process

https://www.rambus.com/blogs/rambus-launches-r-28g-serial-link-phy-on-samsungs-14nm-lpp-process-2/

Rambus has launched a 28Gbps multi-modal serial link PHY on Samsung’s leading-edge 14nm Low Power Plus (LPP) process. According to Luc Seraphin, senior VP and GM of Rambus’ Memory and Interfaces division, the R+ 28G Serial Link PHY is a100 Gigabit Ethernet solution optimized for power and area efficiency in long-reach channels. “The increasing demand […]

Rambus Announces R+™ 28G Serial Link PHY on Samsung 14nm LPP Process

https://www.rambus.com/rambus-announces-r-28g-serial-link-phy-on-samsung-14nm-lpp-process/

Rambus Announces R+™ 28G Serial Link PHY on Samsung 14nm LPP Process Comprehensive IP solution enables high performance for networking and data center applications SUNNYVALE, Calif. – January 19, 2016 – Rambus Inc. (NASDAQ:RMBS) today announced the availability of a 28Gbps multi-modal serial link PHY on Samsung’s leading-edge 14nm Low Power Plus (LPP) process. The […]

MStar, Intertrust and Rambus to Showcase an Integrated, End-to-end Security Solution for 4K UHD TVs at IBC 2015

https://www.rambus.com/mstar-intertrust-and-rambus-to-showcase-an-integrated-end-to-end-security-solution-for-4k-uhd-tvs-at-ibc-2015/

Joint solution delivers industry leading hardware-based security for connected TVs AMSTERDAM and SUNNYVALE, Calif. —September 9, 2015 — MStar Semiconductor, Inc., a leading provider of display and digital home solutions, today announced it has started production of a secure chipset for connected TVs that integrates the Rambus Cryptography Research CryptoFirewall™ security core with Intertrust’s ExpressPlay™ […]

FlexClocking™ Architecture

https://www.rambus.com/flexclocking-architecture/

Traditional, multi-gigahertz memory interfaces require timing synchronization circuitry in both the controller and memory interface in order to compensate for any skew that arises between clock, data, and command/address (C/A) signals. FlexClocking™ Architecture technology is an architecture that utilizes asymmetric partitioning and places critical calibration and timing circuitry in the controller interface, greatly simplifying the […]

Google wants 5 petabit switching

https://www.rambus.com/blogs/mid-google-wants-5-petabit-switching/

The Platform’s Timothy Prickett Morgan reports that Google is eyeing networking throughput capabilities of 5 petabits per second. However, as Google Fellow Amin Vahdat recently pointed out, the industry currently “underprovisions” networks because it doesn’t (yet) know how to build big networks capable of delivering “lots” of bandwidth. According to Vahdat, the ideal network should […]

Leadership

https://www.rambus.com/leadership/

Leadership Explore Rambus Luc Seraphin President & CEO Sean Fan SVP & COO Kit Rodgers SVP, Technology Partnerships & Corporate Development John Shinn SVP & General Counsel Cliff Burnette SVP & CHRO Tina Faris VP, Chief of Staff & Deputy General Counsel Jeffry Moore, Ph.D. SVP, Global Operations I Nong Chao SVP, IC Operations Desmond […]

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