ContactChaCha20 family of accelerators.
Supporting TLS1.3 IoT HomeKit.
At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
ChaCha-IP-13 ChaCha20 Accelerators
The ChaCha-IP-13 (EIP-13) is an IP solution for accelerating the ChaCha20 cipher algorithm (RFC7539), supporting the NIST CTR mode up to 12.8 Gbps @ 300MHz. Designed for fast integration, low gate count and full transforms, the ChaCha-IP-13 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high-speed crypto pipelines.
Available in three configurations / performance grades.
How the ChaCha-IP-13 ChaCha20 Accelerators work
The ChaCha-IP-13 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). For example, the ChaCha-IP-13 is the cipher core embedded in the VaultIP root of trust security cores providing support for TLS1.3 and HomeKit IoT applications (ChaCha20 is also available as SW implementation in VaultIP cores). The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.
Sustained performance for any object sizes ranges from 2 to 12.8 Gbps depending on the configuration and area. Gate count is around 30K gates depending on the configuration.
Rambus also offers the required Poly1305 algorithm to match the ChaCha20 cipher in HomeKit.
Anti-Tampering Technologies
The design of chip anti-tamper protection needs to adapt and scale with rising threats. Adversaries range from high school hackers to well-funded state actors. Given the threats, it’s useful to think about anti-tamper countermeasures as a hierarchy of safeguards that parallel the type, effort and expense of attacks. Watch this webinar to learn the eleven kinds of tampering attacks and their required skills and resources, and countermeasures for each of these attacks.
ChaCha-IP-13 Information
Key benefits:
- Silicon-proven implementation
- Fast and easy to integrate into SoCs
- Flexible layered design
- Complete range of configurations
- World-class technical support
Features:
- Wide bus interface (512-bit data, 256-bit keys) or 32-bit register interface
- Key sizes: 128 and 256 bits
- Includes key scheduling hardware
- Feedback mode CTR.
- Low speed (High Frequency), Medium Speed, High Speed versions
- Fully synchronous design
Introduction to Side-Channel Attacks
Side-channel attacks conducted against electronic gear are relatively simple and inexpensive to execute. Such attacks include simple power analysis (SPA) and Differential Power Analysis (DPA). As all physical electronic systems routinely leak information, effective side-channel countermeasures should be implemented at the design stage to ensure protection of sensitive keys and data.
