Data centers continue to adopt full line-rate security at various levels and use cases. Layer 2 (MACsec) and Layer 3 (IPsec) protocols are used to protect either full links or specific subnets or even customer-driven virtual networks. The integration of multiple security protocols is becoming an important requirement for data center silicon that aims to support multiple use cases. Join Maxim Demchenko to learn about the requirements for adding MACsec/IPsec into data center silicon designs.
Webinars
Inline Memory Encryption to Enable Confidential Computing for Data Center Designs
There is a growing industry consensus on the imperative of incorporating memory encryption in computing architectures for protecting data in use. Designing and implementing a secure memory encryption system can be complex and comes with unique challenges from both the memory and security technology perspectives. Join Ajay Kapoor to learn how memory encryption can be used in your next data center design to enable confidential computing.
Securing the Semiconductor Supply Chain with Silicon Provisioning and Cloud Key Management
The semiconductor industry is the lifeblood of the digital economy. The design, manufacturing and consumption of chips is a global ecosystem, and competition is fierce as scaling and cost reductions based on Moore’s law are diminishing. Counterfeit and other unauthorized chips create real risks in areas of reliability, functionality, performance and safety. This presentation will discuss how semiconductor companies can protect their IP and business by securely provisioning silicon, and the means to provide the ecosystem-wide capabilities needed to verify the identity and provenance of semiconductor devices.
High-Performance AI/ML Inference with 24G GDDR6 Memory
This webinar will explore how GDDR6, operating at data rates up to 24 Gigabits per second (Gb/s) supports the memory and performance requirements of AI/ML inference workloads through an excellent combination of high bandwidth and low latency performance. Frank Ferro and Vinitha Seevaratnam will also discuss the design and implementation considerations of GDDR6 memory subsystems with a particular emphasis on signal integrity challenges at ultra-high data rates.
Accelerating Data Interconnects with PCI Express 6.0 Interface IP
The latest generation of PCI Express® (PCIe®) 6.0, advances performance to 64 GT/s in support of advanced data center workloads and networking. In this presentation, interface technology expert Lou Ternullo will discuss the new features implemented in PCIe 6.0, such as PAM4 signaling and low-latency forward error correction (FEC). He will also show how the Rambus PCIe interface IP can support your future design requirements.
Automotive Security: Meeting the Growing Challenges
Vehicle systems and the semiconductors used within them represent some of today’s most complex electronics. In the drive to autonomous vehicles, increasingly sophisticated electronic systems are being developed for powertrain and vehicle dynamics, advanced driver assistance systems (ADAS), vehicle-to-everything (V2E) connectivity, infotainment, and in-vehicle experience. In addition to achieving higher levels of performance, these systems must meet automotive functional safety requirements as specified by ISO 26262.
