This webinar will examine two critical technologies that address these challenges: Inline Memory Encryption (IME) and MACsec (Media Access Control Security).
Protocol Engines
The Ultimate Guide to Secure Silicon: MACsec & IPsec
The Ultimate Guide to Secure Silicon webinar series focuses on cutting-edge design and implementation techniques for hardware security. This series is perfect for engineers and designers looking to strengthen their knowledge, stay current with the latest hardware security advancements and learn more about security IP solutions. This webinar will be focused on MACsec & IPsec, presented by Maxim Demchenko, Technical Director at Rambus.
Protecting Devices and Data in the Quantum Era
Quantum computers will eventually become powerful enough to break traditional asymmetric cryptographic methods, that is, some of the most common security protocols used to protect sensitive electronic data. This presentation will highlight the recent developments in post-quantum cryptography and discuss how designers can get ready for the quantum era.
Securing MCUs with SCA Protection in IoT Designs
A side-channel attack (SCA) is a security exploit that attempts to extract secrets from a chip or a system. This presentation will give an overview of some of the most common types of SCA and highlight the countermeasures that designers can implement to diminish risk in low-power IoT designs.
The Convergence of MACsec and IPsec in Data Center Silicon Designs
Data centers continue to adopt full line-rate security at various levels and use cases. Layer 2 (MACsec) and Layer 3 (IPsec) protocols are used to protect either full links or specific subnets or even customer-driven virtual networks. The integration of multiple security protocols is becoming an important requirement for data center silicon that aims to support multiple use cases. Join Maxim Demchenko to learn about the requirements for adding MACsec/IPsec into data center silicon designs.
Memory Encryption Solutions for Protecting Data in Use
There are many challenges to achieving good “memory security,” especially in that the term “memory” could refer to on-chip SRAM, embedded non-volatile memory, or even off-chip memory (e.g., both DRAM or mass-storage non-volatile). We refer to data within non-executable NVM to be “data at rest,” while data within volatile memory like SRAM or DRAM to be “data in use.” In both domains, data within these memories is of interest to an adversary – it has either immediate value (e.g., passwords, secret keys, AI/ML datasets, etc.), or it can indirectly lead to exposure of those valuable assets. This presentation will focus on the key aspects of memory security for data-in-use applications: 1) data privacy, 2) data authenticity, and 3) data freshness, and how those security aspects weigh against critical performance metrics including latency and memory overhead.
