At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.
DDR5 Multiplexed Registering Clock Driver (MRCD) and Multiplexed Data Buffer (MDB)
Delivering industry-leading memory bandwidth and capacity
The Rambus DDR5 Multiplexed Registering Clock Driver (MRCD) and Multiplexed Data Buffer (MDB) enable industry-standard DDR5 Multiplexed Rank DIMMs (MRDIMMs) operating at data rates up to 12,800 MT/s.
| Description | Part Number | Product Brief | Applications |
|---|---|---|---|
| 12800 MT/s Multiplexed Registering Clock Driver | D5MRCD2Gxx |  |
Server MRDIMM 12800 |
| 12800 MT/s Multiplexed Data Buffer | D5MDB2XGxx | |
Server MRDIMM 12800 |
Each DDR5 MRDIMM 12800 requires one MRCD and ten MDB chips to multiplex the memory channel. The MRCD and MDB will also support a Tall MRDIMM form factor with four ranks of DDR5 DRAMs for double the capacity of a dual-rank RDIMM in a cost-effective manner.
Expanding Server Memory Capabilities with Multiplexed Rank DIMM (MRDIMM) Technology
As per socket compute density increases, the amount of directly accessible, low-latency memory bandwidth and capacity to adequately feed data to the multiple cores needs to scale accordingly. Scaling memory bandwidth by increasing raw DRAM component bandwidth or by increasing the number of memory channels has challenges and is reaching limits. JEDEC has unveiled the development of a new DIMM technology called Multiplexed Rank Dual Inline Memory Modules (MRDIMM) to address the bandwidth challenge.
Data Center Evolution: DDR5 DIMMs Advance Server Performance
Agentic AI is reshaping data center architectures, introducing persistent, memory-intensive workloads that demand unprecedented bandwidth, capacity, and efficiency from system memory. Unlike traditional AI/ML pipelines, agentic systems operate in continuous, context-rich loops that amplify the importance of main memory as a critical performance enabler. This white paper explores how DDR5 DIMMs address these emerging requirements, delivering significant advancements in data rate, density, power efficiency, and channel architecture over DDR4. It examines the role of DDR5 as the foundational memory layer in modern AI infrastructure, complementing heterogeneous compute architectures and supporting highly concurrent, data-driven workloads, while also outlining the key design considerations required to achieve reliable, high-performance operation in next-generation servers.
