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FLIT (Flow Control Unit)

Table of Contents

  1. Definition
  2. How it Works
  3. Features
  4. Benefits
  5. Enabling Technologies
  6. Rambus Technologies

What is a FLIT?

A FLIT (Flow Control Unit) is the smallest unit of data transmission in packet-switched networks, particularly in high-speed interconnect protocols like Compute Express Link (CXL) and PCI Express (PCIe). FLITs are fixed-size segments that encapsulate portions of a larger packet, enabling efficient and deterministic data flow across complex interconnect fabrics.

How FLIT works

In modern interconnect architectures, data is transmitted in packets. These packets are broken down into FLITs to facilitate flow control, buffer management, and error detection. Each FLIT contains control information, payload data, and sometimes error-checking codes. The use of FLITs allows the system to manage congestion, prioritize traffic, and ensure reliable delivery even in multi-hop or multi-device environments.

For example, in CXL 3.0, FLITs are 256 bytes long and are used to carry memory and I/O transactions between CPUs, accelerators, and memory expanders. The fixed size simplifies hardware design and improves predictability in latency-sensitive applications.

What are the key features of FEC?

  • Fixed-size data units (e.g., 256 bytes in CXL 3.0)
  • Used in layered protocol stacks (e.g., physical, data link, transaction layers)
  • Supports priority-based routing and traffic shaping
  • Compatible with advanced error correction (e.g., FEC, ECRC)
  • Enables multi-device and multi-host communication
 

What are the benefits of FEC?

  • Deterministic Latency: Fixed-size FLITs enable predictable timing and performance.
  • Efficient Flow Control: Simplifies buffer allocation and congestion management.
  • Scalable Communication: Supports high-throughput, low-latency data exchange across complex topologies.
  • Enhanced Reliability: Facilitates error detection and recovery mechanisms.
 

Enabling Technologies

FLIT-based architectures are foundational in:

  • CXL 2.0/3.0 for memory pooling and coherent cache sharing
  • PCIe 6.0 with FLIT mode for high-speed data transfer
  • Network-on-Chip (NoC) designs in SoCs and data centers
  • High-performance computing (HPC) and AI/ML accelerators
 

Rambus Technologies

Rambus offers CXL 2.0/3.0 Interface IP and PCIe 6.0 Controller IP that support FLIT-based data transmission. These IP cores are designed for ultra-low latency and high bandwidth, making them ideal for next-generation data center, AI, and memory expansion applications. Rambus also integrates Forward Error Correction (FEC) and End-to-End CRC (ECRC) to ensure robust FLIT-level data integrity.

Click here to see L0p and Flit mode in action in PCIe 6.x here.

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