Bart Stevens, Senior Director of Product Marketing for Security IP, discusses the security challenges of AI inference processing in both cloud-based data centers and edge devices. He emphasizes the need for robust security measures to protect valuable AI models and sensitive data across various deployment environments. He covers essential cryptographic principles, confidential computing, and key security mechanisms such as data at rest, in use, and in motion protection. Bart highlights the differences in security requirements between data centers and edge devices due to operational constraints and threat models.
From Training to Inference: HBM, GDDR & LPDDR Memory
Nidish Kamath, director of product management for Rambus Memory Controller IP, discusses the company’s HBM, GDDR, and LPDDR solutions that address AI training and inference workload requirements. Nidish explains the differences between AI training and inference, highlighting the unique compute and memory needs of each. He will delve into the architectural innovations of HBM, including its 2.5D and 3D memory architecture, and the evolution of HBM memory to meet AI demands. Additionally, Nidish will cover advancements in GDDR and LPDDR memory technologies, emphasizing their roles in AI inference and mobile devices.
Navigating the Dynamics of IP Licensing for Data Center & AI
Raj Uppala, Senior Director of Marketing and Partnerships at Rambus, explores the complexities of IP licensing for emerging data center and AI applications. He discusses the growing demand for specialized IP components such as memory controllers, security solutions, and high-performance interfaces driven by the rise of AI accelerators and SoCs. Raj highlights the key factors customers consider when evaluating IP solutions, such as time-to-market, scalability, interoperability, and cost-effectiveness. The presentation underscores the importance of choosing the right IP solutions to accelerate innovation and streamline development in high-performance computing and AI infrastructure.
The Road Ahead for Main Memory in the Data Center
Carlos Weissenberg, Product Marketing Manager for Memory Interface Chips at Rambus, discusses the increasing demands for memory driven by AI and high-performance computing. Carlos will explain the innovations incorporated in DDR5 memory modules, such as the dual-channel architecture and improved power management, designed to meet the growing memory requirements of data center servers. He will also discuss how the DDR5 memory interface chipset enables higher performance and greater capacity required by advanced server workloads.
Why Memory Matters for AI
In this roundtable discussion, memory experts Steve Woo, John Eble, and Nidish Kamath explore the critical role of memory in AI applications. They discuss how AI’s rapid evolution, especially with the growth of large language models, is driving the need for higher memory capacity, bandwidth, and power efficiency.
HBM4 Controller Product Brief
The Rambus HBM4 Controller is designed to support customers with deploying a new generation of HBM memory for cutting-edge AI accelerators, graphics and high-performance computing (HPC) applications. The Rambus HBM4 Controller supports a data rate of 10 Gigabits per second (Gbps) and delivers a total memory bandwidth of 2,560 Gigabytes per second (GB/s) or 2.56 Terabytes per second (TB/s) of throughput for every attached HBM4 memory device.
