[Live on January 10, 2024] Quantum computers will eventually become powerful enough to break current asymmetric encryption, placing important data and assets at risk. In this presentation, Bart Stevens will discuss recent developments in Quantum Safe Cryptography and highlight what you need to know to protect devices and data in the quantum computing era.
The Rambus Quantum Safe Engine (QSE) IP provides Quantum Safe Cryptography acceleration for ASIC, SoC and FPGA devices. The QSE supports the FIPS 203 ML-KEM and FIPS 204 ML-DSA draft standards. Download the product brief to find out about the QSE features, learn how the QSE can be used for multiple use cases, and review the QSE block diagram.
- Expands industry-leading family of Quantum Safe IP solutions for data center and government hardware security
- Integrates into root of trust or embedded secure element in advanced SoCs and FPGAs
- Delivers cryptographic acceleration with leading NIST-selected quantum-resistant algorithms
SAN JOSE, Calif. – December 4, 2023 – Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced the availability of a Quantum Safe Engine (QSE) for integration into hardware security elements in ASICs, SoCs and FPGAs. Quantum computers will enable adversaries to break current asymmetric encryption, placing important data and assets at risk. The Rambus QSE IP core uses NIST-selected quantum-resistant algorithms to protect valuable data center and government hardware against attacks emerging in the post quantum computing era.
“From AI, to streaming video, to email, the applications we rely on daily depend on the integrity of data and must be guarded against the growing risk of attacks enabled by quantum computers,” said Neeraj Paliwal, general manager of Silicon IP at Rambus. “The Rambus Quantum Safe Engine is another important addition to our security IP portfolio helping customers transition to Quantum Safe Cryptography starting today.”
“Quantum computers will provide individuals and organizations the exponential speed-up and compute power needed to solve some of today’s most complex problems, including the ability to decrypt current data encryption algorithms,” said Heather West, PhD, research manager of Quantum Computing Research at IDC. “Implementing quantum-resistant cryptography now is key for organizations to protect their past, current and future data from quantum computing enabled attacks.”
The Rambus QSE IP is available as a standalone cryptographic core or integrated in the Rambus Quantum Safe Root of Trust IP as a comprehensive hardware security solution. It supports the National Institute of Standards and Technology (NIST) draft standards for quantum-resistant algorithms (FIPS 203 ML-KEM and FIPS 204 ML-DSA), and provides SHA-3, SHAKE-128 and SHAKE-256 acceleration. For highly secure applications requiring additional protection against differential power analysis (DPA) attacks, a DPA version of the QSE IP is available.
Availability and Additional Information:
The Rambus QSE is available for licensing today. Learn more at https://www.rambus.com/security/quantum-safe-cryptography/qse-ip-86/.
The Rambus Compute Express Link (CXL) 3.0 Controller with AXI leverages a silicon-proven PCIe controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard.
The Rambus Compute Express Link (CXL) 3.0 Controller leverages a silicon-proven PCIe controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard.
SAN JOSE, Calif. – November 13, 2023
|What:||Rambus Demonstrates CXL Platform Development Kit Enabling Memory Tiering for AI Infrastructure|
|Who:||Rambus Inc. (Nasdaq: RMBS), a premier chip and silicon IP provider|
|Where:||Supercomputing 2023 (SC23) at the CXL Consortium Booth (Booth #1301) at the Colorado Convention Center in Denver, CO|
|When:||November 14 -16, 2023. Exhibition begins at 10:00 a.m. MT.|
This week at SC23, Rambus will demonstrate a CXL platform development kit (PDK) that enables module and system makers to prototype and test CXL-based memory expansion and pooling solutions for AI infrastructure and other advanced systems. The demonstration will show CXL memory tiering functionality in a production server running industry-standard benchmarking software.
The Rambus CXL PDK is interoperable with CXL 1.1 and CXL 2.0 capable processors and memory from all the major memory suppliers. It leverages today’s available hardware to accelerate the development of the full stack of next-generation CXL-based solutions (device, module, system and software).
The Rambus CXL PDK includes:
- CXL hardware platform (add-in card), featuring Rambus CXL memory controller chip prototype
- Advanced debug and visualization tools
- CXL-compliant management framework and utilities
- Fully customizable SDK for value-added features and vendor-specific commands
Join Rambus at SC23 in the CXL Consortium Booth (Booth 1301) to see the CXL PDK demonstration in action.
To learn more about SC23, visit https://www.rambus.com/event/sc23-supercomputing-2023/. To learn more about the Rambus CXL PDK, visit https://www.rambus.com/cxl-memory-initiative/.