Some of the top Rambus technical experts will hold forth at DesignCon 2019 in a full-day sponsored training session on Wednesday, January 30. Plus, the Rambus booth #837 will demonstrate the company’s developments in GDDR6, as well as its comprehensive suite of Ethernet, PCIe, DDR, and HBM IP cores for today’s most challenging data center and networking applications.
We will also be showcasing our CryptoManager Root of Trust and its multiple roots of trust capability for a connected home application.
Included in the technical talks are a half dozen training sessions designed to help audiences understand the latest advances in Rambus’ IP core product line. They’ll be hearing about achieving better performance and power efficiency in memory systems for AI applications. They’ll also get the basics of reducing power and cost using 112G XSR technology to enable optical communication adoption.
Other Rambus sessions cover future electrical/optical/signal integrity challenges for wireline communication connectivity, memory options for enabling high-performance applications, and design tradeoffs and system/signal integrity challenges for implementing 112G in FinFET technology. Plus, Rambus will devote one of those training sessions to a secure core implementation with a RISC-V CPU.
Rambus’ training sessions schedule follows:
Memory Options for High Performance Applications
Speakers: Sreeja Menon, Principal Engineer IP Cores Architecture
Frank Ferro, Senior Director IP Cores Product Marketing
Time: 9:05AM – 9:45AM
Leading edge high-performance computation power and an exploding digital world is limited by memory speed, access throughput, and latency. This presentation discusses the various options available for enablement of a variety of applications, their characteristics, and tradeoffs.
112Gbps ADC Based Long Reach SerDes
Speaker: Ken Dyer, Director IP Cores Architecture
Time: 10:05AM – 10:45AM
The application of high-speed power-efficient ADC’s in long reach wireline communication circuits will be discussed. Design tradeoffs, and System and Signal Integrity challenges for the implementation of 112Gbps in state-of-the-art FinFET technology will be presented.
Enable Innovation with Hardware-Enforced Security at the Core
Speaker: Ben Levine, Senior Director of Product Management
Time: 11:05 AM – 11:45 AM
Making a highly complex processor optimized for performance, into a secure processor is very difficult. Instead, move security-sensitive code into secure hardware cores siloed from general purpose processors, so the cores can utilize processors optimized for secure operation and implement hardware protection against attacks. See an example of a secure core implemented using a custom-designed RISC-V CPU targeted specifically for security; demonstrating a layered security approach offering robust protection against a broad range of threats through carefully thought out system design.
Memory Systems for AI and Leading-Edge Applications
Speaker: Steven Woo, VP, Systems and Solutions and Distinguished Inventor
Time: 2:00PM – 2:40PM
AI and other leading-edge applications achieve higher performance and power efficiency by combining specialized silicon with well-designed memory systems. These systems must address challenging power and physical-design constraints. This presentation will discuss the crucial role that memory systems play and highlight some of the performance and power-efficiency tradeoffs that architects face when designing memory systems for these applications.
Exploring How 112G XSR Technology Enables Adoption of Optical Communication
Speaker: Mondeep Thiara, Senior IP Cores Product Marketing Manager
Time: 2:50PM – 3:30PM
The evolution of optical modules to on-board optics and co-packaged optics. This talk will discuss how 112G XSR technology and silicon photonics can help lower power and cost, allowing a wider adoption of optical communications in data centers.
Next Generation Wireline Communication Interfaces
Speaker: Saman Sadr, Vice President IP Cores Marketing
Time: 3:45PM – 4:25PM
Electrical, Optical and Signal Integrity challenges of the next generation wireline communication connectivity will be reviewed. Solutions for direct connectivity between Electrical and Optical interfaces will be presented, and 2.5D/3D advanced packaging and fabrication technology requirements will be explored.