The Rambus PCI Express® (PCIe®) 6.0 PHY is a low-power, area-optimized, silicon IP core designed with a system-oriented approach to maximize flexibility and ease of integration. It delivers data rates of up to 64 Gigatransfers per second (GT/s) for AI/ML and other data intensive workloads, and it supports the latest version of the Compute Express Link™ (CXL™) specification, version 3.0. The PCIe 6.0 PHY can be combined with the Rambus PCIe 6.0 Controller to make a complete PCIe 6.0 interface subsystem.
The Rambus PCI Express® (PCIe®) 6.0 interface subsystem is a low-power, area optimized, silicon IP designed with a system-oriented approach to maximize flexibility and ease of integration. It consists of a co-verified PHY and digital controller providing a complete PCIe 6.0 interface subsystem. The subsystem delivers data rates of up to 64 Gigatransfers per second (GT/s) for AI/ML and other data intensive workloads. With optional IDE Engine, the solution offers cutting-edge security to protect valuable data assets.
The Rambus SPD Hub with Internal Temperature Sensor (SPD Hub) SPD5118-G1B enables DDR5 Registered DIMMs (RDIMMs), Load Reduced DIMMs (LRDIMMs), Non-Volatile memory DIMMs (NVDIMMs), Unbuffered DIMMs (UDIMMs) and Small-Outline DIMMs (SODIMMs).
The Rambus Temperature Sensor (TS) TS5110-G1B enables DDR5 Registered DIMMs (RDIMMs), Load Reduced DIMMs (LRDIMMs) and Non-Volatile memory DIMMs (NVDIMMs). Two TS are used per DIMM which along with the SPD Hub’s internal TS provide three points of thermal telemetry.
The MACsec-IP-361 is a plug-and-play solution for adding MACsec on the xMII side of an Ethernet subsystem. It is ideally positioned for designs where the MAC function is tightly integrated with the system-side, for example DMA-MAC Ethernet controllers or switch core IP with integrated MAC modules.
The Rambus PCIe 6.0 Retimer Controller provides a highly optimized low-latency data path for signal regeneration. It supports retimer chip PHYs via PIPE 5.2/6.1 interfaces. The control plane interface is provided via CSR (AHB-lite). The PCIe 6.0 Retimer Controller is CXL protocol aware and supports links using 64 GT/s and lower data rates of PCIe.