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TLP (Transaction Layer Packet)

Table of Contents

  1. Definition
  2. How it Works
  3. Features
  4. Benefits
  5. Enabling Technologies
  6. Rambus Technologies

What are Transaction Layer Packets (TLP)?

A Transaction Layer Packet (TLP) is the fundamental unit of communication in the PCI Express (PCIe) protocol, used to encapsulate data and control information exchanged between devices. TLPs are generated and processed at the Transaction Layer of the PCIe stack and are responsible for carrying out all high-level PCIe operations, including memory reads/writes, I/O transactions, and configuration accesses

How TLPs works

TLPs are constructed by the Transaction Layer and passed down to the Data Link Layer, which appends a Link CRC (LCRC) for error detection. The Physical Layer then serializes the packet for transmission. Each TLP includes a header, optional data payload, and end-to-end CRC (ECRC) for integrity checking. The header contains fields such as:

  • Packet type (e.g., memory read, memory write, I/O read/write)
  • Addressing information
  • Requester and completer IDs
  • Length and attributes

TLPs are categorized into three main types:

  • Memory Transactions – for reading/writing system memory
  • I/O Transactions – for legacy I/O space access
  • Configuration Transactions – for device setup and management

What are the key features of TLPs?

  • Variable-length payloads (up to 4 KB in PCIe Gen 3 and beyond)
  • 3DW or 4DW headers depending on address size
  • Optional ECRC for end-to-end data integrity
  • Support for atomic operations, message signaling, and interrupts (MSI/MSI-X)
  • Compatibility with multi-function and virtualized devices
 

What are the benefits of TLPs?

TLPs enable efficient, scalable, and reliable communication in PCIe systems by:

  • Supporting packet-based communication for high-speed serial links
  • Enabling flexible addressing and data payload sizes
  • Facilitating error detection with ECRC and LCRC
  • Allowing split transactions for improved throughput
  • Supporting virtual channels and QoS policies
 

Enabling Technologies

TLPs are central to:

  • PCIe 3.0/4.0/5.0/6.0 interconnects
  • CXL (Compute Express Link), which builds on PCIe for memory and cache coherency
  • High-speed SerDes PHYs for serial data transmission
  • Advanced Error Reporting (AER) and flow control mechanisms
  • Multi-root and peer-to-peer PCIe topologies

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